Preemptive multitasking on FPGAs

IEEE Symposium on FPGAs for Custom Computing Machines, Proceedings

Volumn 2000-January, Issue , 2000, Pages 301-302

  Levinson, L ^b   Manner R ^a   Sessler, M ^a   Simmler, H ^a  

^a UNIVERSITY OF MANNHEIM   (Germany)

^b WEIZMANN INSTITUTE OF SCIENCE   (Israel)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER OPERATING SYSTEMS; COMPUTERS; MULTITASKING; RECONFIGURABLE ARCHITECTURES; RECONFIGURABLE HARDWARE; TIME SHARING SYSTEMS;

CO-PROCESSOR ARCHITECTURE; CONVENTIONAL COMPUTERS; PREEMPTIVE MULTITASKING; RECONFIGURABLE COMPUTING; RUN-TIME CONFIGURATION;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 62349131597     PISSN: 10823409     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FPGA.2000.903426     Document Type: Conference Paper

References (4)

1. Optimagic WebSide: Board List, 2000. http://www.optimagic.com/boards.html
2. R. Hudson, et.al.: A Run-Time Reconfigurable Engine for Image Interpolation, IEEE Symposium on FPGAs for CCMs, 1998. Page 88-95.
3. G. Brebner: The Swappable Logic Unit: A Paradigm for Virtual Hardware, IEEE Symposium on FPGAs for CCMs, 1997. Pages 77-86.
4. J. Jean et.al.: Dynamic Reconfiguration to Support Concurrent Applications, IEEE Symposium on FPGAs for CCMs, 1998. Pages 302-303.