A 5GbpsC CMOS frequency tolerant multi phase clock recovery circuit

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue CIRCUITS SYMP., 2002, Pages 82-83

  Iwata, Toru ^a   Hirata, Takashi ^a   Sugimoto, Hirokazu ^a   Kimura, Hiroshi ^a   Yoshikawa, Takefumi ^a  

^a PANASONIC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

BIT ERROR RATE; BUFFER CIRCUITS; CMOS INTEGRATED CIRCUITS; INTEGRATED CIRCUIT MANUFACTURE; INTEGRATED CIRCUIT TESTING; INTERFACES (COMPUTER); PHASE LOCKED LOOPS; VARIABLE FREQUENCY OSCILLATORS;

CLOCK AND DATA RECOVERY CIRCUIT; DELAY PATH SELECTORS; MULTI PHASE GATED VARIABLE CONTROLLED OSCILLATORS; PLESIOCHRONOUS CLOCKING;

TIMING CIRCUITS;

EID: 0242443400     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)

1. J. Savoj, B. Razavi, "A 10-Gb/s CMOS Clock and Data Recovery Circuit", Digest of Symposium on VLSI Circuits, pp.136-139, June, 2000
2. M. Nakamura, N. Ishihara, Y. Akazawa, "A 156 Mbps CMOS Clock Recovery Circuit for Burst-mode Transmission", Digest of Symposium on VLSI Circuits, pp.122-123, June, 1996
3. T. Yoshikawa et al., "A 1.25Gb/s CMOS Receiver Core with Plesiochronous Clocking Capability for Asynchronous Burst Data Acquisition", Digest of IEEE International Solid-State Circuit Conference, pp.254-255, Feb., 2000