Packaging provides viable alternatives to SOC

Semiconductor International

Volumn 23, Issue 8, 2000, Pages 169-170,-174,-178,-181

  Baliga, John ^a  

^a NONE

Author keywords

[No Author keywords available]

Indexed keywords

COST BENEFIT ANALYSIS; ELECTRONICS PACKAGING; MASKS; MICROELECTROMECHANICAL DEVICES; MICROPROCESSOR CHIPS; MULTICHIP MODULES; RELIABILITY; SEMICONDUCTING FILMS; SEMICONDUCTING GALLIUM ARSENIDE; SEMICONDUCTING SILICON; SEMICONDUCTOR DEVICES; YIELD STRESS;

SINGLE LAYER INTEGRATED MODULE; STACKED DIE PACKAGING; SYSTEM IN A PACKAGE; SYSTEM ON A CHIP;

INTEGRATED CIRCUIT LAYOUT;

EID: 6744237810     PISSN: 01633767     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

References (7)

1. 1999 International Technology Roadmap for Semiconductors.
2. R R. Tummala, "SOP vs. SOC: Needs, Challenges and Status," 2000 European VLSI Packaging and Microsystem Packaging Techniques and Manufacturing Technologies Workshop, May 8-9, 2000, Cork, Ireland
3. E. Davidson, "Large Chip vs. MCM for a High-Performance System," IEEE Micro, July/August 1998, pp. 33-41.
4. L. Schaper, "Ultimate Packaging: The Limits of Density," Keynote presentation, HD International, Denver.
5. K. Vaesen, S. Donnay, P. Pieters, G. Carchon, W. Diels, P. Wambacq, W. DeRaedt, E. Beyne, M. Engles, I. Bolsens, "Chip-Package Co-design of a 4.7 GHz VCO," Proceedings of the 2000 International Conference on High Density Interconnect and Systems Packaging, Denver, April 25-28, 2000, p. 301-6.
6. J. Baliga, "MCM Has Chips in Redistribution," Semiconductor International, February 2000, p. 64.
7. T. Ishida, "A Vision of Electronics in the 21st Century," Proceedings of the Technical Program, Fifth Annual Pan Pacific Microelectronics Symposium, January 2000.