A methodology for the interconnect performance evaluation of 2D and 3D processors with memory

Proceedings of the IEEE 2002 International Interconnect Technology Conference, IITC 2002

Volumn , Issue , 2002, Pages 164-166

  Chandra, G ^a   Kapur, P ^a   Saraswat, K C ^a  

^a STANFORD UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

STOCHASTIC MODELS; STOCHASTIC SYSTEMS; THREE DIMENSIONAL INTEGRATED CIRCUITS;

3-D INTEGRATION; 3D PROCESSORS; INTERCONNECT PERFORMANCE; LARGE AMOUNTS; LAYOUT CONSIDERATIONS; ON CHIP MEMORY; RANDOM LOGIC; WIRE LENGTH DISTRIBUTION MODEL;

INTEGRATED CIRCUIT INTERCONNECTS;

EID: 84961724195     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IITC.2002.1014921     Document Type: Conference Paper

References (5)

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3. J. A. Davis, V. K. De and J. D. Meindl, A Stochastic wire length distribution for Gigascale Integration (GSI) - Part I, IEEE Trans. Electron Devices, March 1998
4. J. A. Davis et al, Interconnect limits on GSI in the 21st Century, Proceedings of the IEEE, March 2001
5. J. A. Davis, V. K. De and J.D. Meindl, A Stochastic wire length distribution for Gigascale Integration (GSI) - Part II, IEEE Trans. Electron Devices, March 1998