Dual-Vdd interconnect with chip-level time slack allocation for FPGA power reduction

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 25, Issue 10, 2006, Pages 2023-2034

  Lin, Yan ^a,b   He, Lei ^a,b  

^a IEEE   (United States)

^b UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

Interconnect; Low power design; Optimization; Power minimization

Indexed keywords

INTERCONNECTS; LOW-POWER DESIGN; POWER MINIMIZATION; TREE-BASED LEVEL CONVERTER INSERTION (TLC);

ALGORITHMS; ANALOG TO DIGITAL CONVERSION; ELECTRIC POWER MEASUREMENT; FIELD EFFECT TRANSISTORS; FIELD PROGRAMMABLE GATE ARRAYS; LEAKAGE CURRENTS; MICROELECTRONICS; OPTIMIZATION; TREES (MATHEMATICS);

OPTICAL INTERCONNECTS;

EID: 33748286948     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2006.870858     Document Type: Article

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