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IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers

Volumn , Issue , 2003, Pages 813-817

Minimum-Area Sequential Budgeting for FPGA

(2) Yeh, Chao Yang a Marek Sadowska, Malgorzata a

a University of California (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; APPLICATION SPECIFIC INTEGRATED CIRCUITS; COMBINATORIAL CIRCUITS; CONSTRAINT THEORY; FLIP FLOP CIRCUITS; OPTIMIZATION; SCHEDULING; SEQUENTIAL CIRCUITS; VLSI CIRCUITS;

DELAY BUDGETING; SEQUENTIAL BUDGETING ALGORITHMS;

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 0346148438 PISSN: 10923152 EISSN: None Source Type: Conference Proceeding
DOI: None Document Type: Conference Paper

Times cited : (4)

References (9)

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2
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- (1997) IEEE Transactions on Computer Aided Design , vol.16 , Issue.11 , pp. 1332-1341
- Knol, D.¹ Tellez, G.² Sarrafzadeh, M.³

3
- 0020716303
- Optimizing Synchronous Systems
- C. E. Leiserson and J. B. Saxe, "Optimizing Synchronous Systems", In Journal of VLSI and Computer Systems, pp. 41-67, 1983.
- (1983) Journal of VLSI and Computer Systems , pp. 41-67
- Leiserson, C.E.¹ Saxe, J.B.²

4
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- An improved algorithm for minimum-area retiming
- N. Maheshwari and S. S. Sapatnekar, "An improved algorithm for minimum-area retiming", Design Automation Conf., 1997.
- (1997) Design Automation Conf.
- Maheshwari, N.¹ Sapatnekar, S.S.²

5
- 0024716080
- Generation of performance constraints for layout
- R. Nair, C. L. Berman, P. S. Hauge, and E. J. Yoffa, "Generation of performance constraints for layout", IEEE Trans. Computer Aided Design, vol 8, pp 860-874, 1989.
- (1989) IEEE Trans. Computer Aided Design , vol.8 , pp. 860-874
- Nair, R.¹ Berman, C.L.² Hauge, P.S.³ Yoffa, E.J.⁴

6
- 0031377951
- Continuous Retiming: Algorithms and Applications
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- (1997) International Conf. on Computer Design
- Pan, P.¹

7
- 0030260869
- Utilizing the Retiming-Skew Equivalence in a Practical Algorithm for Retiming Large Circuits
- Oct
- S. S. Sapatnekar, R. B. Deokar, "Utilizing the Retiming-Skew Equivalence in a Practical Algorithm for Retiming Large Circuits", IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, vol 15, no 10, pp 1237-1248, Oct, 1996.
- (1996) IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems , vol.15 , Issue.10 , pp. 1237-1248
- Sapatnekar, S.S.¹ Deokar, R.B.²

8
- 0034159552
- Integration of retiming with architectural floor planning
- A. Tabbara, B. Tabbara, R. K. Brayton, A. R. Newton, "Integration of retiming with architectural floor planning", Integration the VLSI journal, 29, pp 25-43, 2000
- (2000) Integration the VLSI Journal , vol.29 , pp. 25-43
- Tabbara, A.¹ Tabbara, B.² Brayton, R.K.³ Newton, A.R.⁴

9
- 0043136763
- Delay Budgeting in Sequential Circuit with Application On FPGA Placement
- C.-Y. Yeh and M. Marek-Sadowska, "Delay Budgeting in Sequential Circuit with Application On FPGA Placement", Design Automation Conf., 2003.
- (2003) Design Automation Conf.
- Yeh, C.-Y.¹ Marek-Sadowska, M.²

* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.