Transient simulation of wire pull test on Cu/Low-K wafers

IEEE Transactions on Advanced Packaging

Volumn 29, Issue 3, 2006, Pages 631-638

  Yeh, Chang Lin ^a   Lai, Yi Shao ^a   Kao, Chin Li ^a  

^a ADVANCED SEMICONDUCTOR ENGINEERING INC   (Taiwan)

Author keywords

Cu low K; Finite element analysis; Wire pull test; Wirebonding

Indexed keywords

BONDING; COMPUTER SIMULATION; COPPER; FINITE ELEMENT METHOD; FRACTURE; GOLD; INTEGRATION; RESIDUAL STRESSES; WIRE; YIELD STRESS;

TRANSIENT SIMULATION; WIRE PULL TEST; WIREBONDING;

NUMERICAL ANALYSIS;

EID: 33747587263     PISSN: 15213323     EISSN: None     Source Type: Journal    
DOI: 10.1109/TADVP.2006.875081     Document Type: Article

References (11)

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