Integration of organic low-k material with Cu-damascene employing novel process

Proceedings of the IEEE 1998 International Interconnect Technology Conference, IITC 1998

Volumn 1998-June, Issue , 1998, Pages 131-133

  Ikeda, Wasanobu ^a   Kudo, Hiroshi ^a   Shinohara, Rika ^a   Shimpuku, Fumihiko ^a   Yamadal, Masao ^a   Furumura, Yuji ^a  

^a Limited 1 2nd Device Development Department   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

INTEGRATED CIRCUIT INTERCONNECTS; ULSI CIRCUITS;

CU DAMASCENE; CU METALLIZATION; HARD MASKS; INTEGRATION PROCESS; INTER-LAYER DIELECTRICS; LOW DIELECTRIC CONSTANTS; ORGANIC LOW-K; ULTRA LARGE SCALE INTEGRATED;

LOW-K DIELECTRIC;

EID: 28944432377     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IITC.1998.704771     Document Type: Conference Paper

References (11)

1. [l] M. T. Bohr, "Interconnect scaling-The real limiter to high performance ULSI", IEDM Tech. Dig., (1995), p.241.
2. H. Miyajima. et al. 16th Symp. Dry Process (1994)
3. S. Takeishi et ai, Plasma-enhanced chemical vapor deposition of fluorocarbon films with high thermal resistance and low dielectric constants, J. Electrochem. SOC, 144, 1997, 1797.
4. J. Wary et al., "Vacuum-deposited parylene AF4: A thermally stable, low dielectric constant polymer for interlayer dielectrics use", DUMIC, (1996), p.207.
5. T. Ranios et al Nanoporous silica for dielectric constant less than 2", ULSI W Muter. s. SOC (1997), p.455.
6. Y. Igarashi et al., "High reliability copper interconnects through dry etching process", SSDM, (1995), p.943.
7. S. C. Sun et al., "Performance of MOCVD tantalum nitride diffusion barrier for copper metallization", VWI Symp., (1995), p.29.
8. S. Venkatesan et al., "A high performance 1.8 V, 0.20p m CMOS technology with copper metallization" , lEDM Tech. Dig., f1997), p.769.
9. D. Edelstein et al., "Full copper wiring in a sub-0.25 p m CMOS ULSI technology", IEDM Tech. Dig., (1997), p.773.
10. Y. Hayashi et al., " A new two-step metal CMP technique for a high performance multilevel interconnects featured by AI-and "Cu in low E , organic film"-metallizations", VLSI Tech. Dig., (1996). p.88.
11. H. Aoki et al., "A degradation-free Cu/HSQ damascene technology using metal mask patterning and post-CMP cleaning by electrolytic ionized water, IEDM Tech. Dig., (1997). p.777.