Fully process-compatible layout design on bond pad to improve wire bond reliability in CMOS ICs

IEEE Transactions on Components and Packaging Technologies

Volumn 25, Issue 2, 2002, Pages 309-316

  Ker, Ming Dou ^a,b   Peng, Jeng Jie ^a,c  

^a IEEE   (Taiwan)

^b NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

^c INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE   (Taiwan)

Author keywords

Ball shear test; Bond pad; Bond wire; Layout; Reliability; TAB; Wire pull test

Indexed keywords

BOND PADS;

CAPACITANCE; FREQUENCIES; INTEGRATED CIRCUIT LAYOUT; RELIABILITY; WIRE;

CMOS INTEGRATED CIRCUITS;

EID: 0036613504     PISSN: 15213331     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAPT.2002.1010022     Document Type: Article

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5. Heel cracking induced by the steep conversion of EMC in large QFP
6. High impact bonding to improve reliability of VLSI die in plastic packages
7. A wire bond reliability model
8. Layout design on bond pads to improve the firmness of bond wire in packaged IC products