A cycle-accurate ISS for a dynamically reconfigurable processor architecture

Proceedings - 19th IEEE International Parallel and Distributed Processing Symposium, IPDPS 2005

Volumn 2005, Issue , 2005, Pages

  Mucci, C ^a   Campi, F ^a,b   Deledda, A ^a   Fazzi, A ^a   Ferri, M ^a   Bocchi, M ^a  

^a UNIVERSITY OF BOLOGNA   (Italy)

^b STMICROELECTRONICS   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

ENERGY CONSTRAINTS; INSTRUCTION SET SIMULATOR (ISS); RECONFIGURABLE PROCESSOR ARCHITECTURES (RA); SYSTEM-ON-CHIP;

DATA FLOW ANALYSIS; EMBEDDED SYSTEMS; LIBRARIES; REAL TIME SYSTEMS;

PROGRAM PROCESSORS;

EID: 33746317587     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IPDPS.2005.14     Document Type: Conference Paper

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