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Volumn , Issue , 2003, Pages 21-29

A pipelined configurable gate array for embedded processors

Author keywords

Energy; FPGA; Pipeline; Reconfigurable processor

Indexed keywords

ALGORITHMS; CMOS INTEGRATED CIRCUITS; EMBEDDED SYSTEMS; ENERGY CONSERVATION; INTEGRATED CIRCUIT LAYOUT; LOGIC DESIGN; PIPELINE PROCESSING SYSTEMS; SILICON ON INSULATOR TECHNOLOGY; VERY LONG INSTRUCTION WORD ARCHITECTURE;

EID: 0037673297     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/611817.611822     Document Type: Conference Paper
Times cited : (25)

References (18)
  • 1
    • 0038256761 scopus 로고    scopus 로고
    • Tensilica Inc.
    • Tensilica Inc. http://www.tensilica.com. 2001.
    • (2001)
  • 3
    • 0027561268 scopus 로고
    • Processor reconfiguration through instruction-set metamorphosis
    • March
    • P. Athanas and H. Silverman. Processor reconfiguration through instruction-set metamorphosis. IEEE Computer, 26(3):11-18, March 1995.
    • (1995) IEEE Computer , vol.26 , Issue.3 , pp. 11-18
    • Athanas, P.1    Silverman, H.2
  • 4
    • 0029368713 scopus 로고
    • Spyder: A SURE (SUperscalar and REconfigurable) processor
    • C. Iseli and E. Sanchez. Spyder: a SURE (SUperscalar and REconfigurable) processor. Journal of Supercomputing, 9(3):231-252, 1995.
    • (1995) Journal of Supercomputing , vol.9 , Issue.3 , pp. 231-252
    • Iseli, C.1    Sanchez, E.2
  • 11
    • 0034174174 scopus 로고    scopus 로고
    • The garp architecture and C compiler
    • April
    • T. Callahan, J. Hauser, and J. Wawrzynek. The Garp architecture and C compiler. IEEE Computer, 33(4):62-69, April 2000.
    • (2000) IEEE Computer , vol.33 , Issue.4 , pp. 62-69
    • Callahan, T.1    Hauser, J.2    Wawrzynek, J.3
  • 13


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.