Hardening techniques against transient faults for asynchronous circuits

Proceedings - 11th IEEE International On-Line Testing Symposium, IOLTS 2005

Volumn 2005, Issue , 2005, Pages 129-134

  Monnet, Y ^a   Renaudin, M ^a   Leveugle, R ^a  

^a TIMA LABORATORY   (France)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC FAULT CURRENTS; HARDENING; NETWORKS (CIRCUITS);

ASYNCHRONOUS CIRCUITS; CIRCUIT BEHAVIOR; QUASI DELAY INSENSITIVE (QDI) CIRCUITS; TRANSIENT FAULTS;

TRANSIENTS;

EID: 33745499420     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IOLTS.2005.30     Document Type: Conference Paper

References (8)

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2. D. Alexandrescu, L. Anghel, M. Nicolaidis, "New methods for evaluating the impact of single event transients in VDSM ICs", The IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, Vancouver, Canada, November 6-8, 2002, IEEE Computer Society Press, Los Alamitos, California, 2002, pp. 99-107.
3. M. Sonza-Reorda, M. Violante, "Accurate and efficient analysis of single event transients in VLSI circuits", 9th IEEE International On-Line Testing symposium, Kos, Greece, July 7-9, 2003, pp. 101-105.
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6. C. LaFrieda, R.Manohar, "Fault Detection and Isolation Techniques for Quasi Delay-Insensitive Circuits", International Conference on Dependable Systems and Networks (DSN'04), Florence Italy, June 28 - July 01, 2004, p.41
7. T. Verdel, Y.Makris, "Duplication-Based Concurrent Error Detection in Asynchronous Circuits: Shortcomings and Remedies", 17th IEEE International Symposium on Defect and Fault Tolerance in VLSI System, 2002, pp. 345-353.
8. S. Moore, R. Anderson, R. Mullins, G. Taylor, J. J. A. Fournier, "Balanced self-checking asynchronous logic for smart card applications", Microprocessors and Microsystems, Elsevier Science Publishers, vol. 27, 2003, pp. 421-430.