Fault detection and isolation techniques for quasi delay-insensitive circuits

Proceedings of the International Conference on Dependable Systems and Networks

Volumn , Issue , 2004, Pages 41-50

  LaFrieda, Christopher ^a   Manohar, Rajit ^a  

^a Cornell University ^*  (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CROSSTALK; ERROR ANALYSIS; FAILURE ANALYSIS; FAULT TOLERANT COMPUTER SYSTEMS; LOGIC CIRCUITS; MATHEMATICAL MODELS; RELIABILITY; SENSITIVITY ANALYSIS; SIGNAL PROCESSING; SPURIOUS SIGNAL NOISE;

ASYNCHRONOUS FAULTS; ERROR PROPAGATION; POWER CONSUMPTION; SYNCHRONIZATION CHANNEL;

NETWORKS (CIRCUITS);

EID: 4544302417     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/dsn.2004.1311875     Document Type: Conference Paper

References (14)

1. M. L. Bushnell and V. D. Agrawal. Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI Circuits. Kluwer Academic Publishers, 2000.
2. P. J. Hazewindus. Testing Delay-Insensitive Circuits. PhD thesis, California Institute of Technology, Pasadena, California, 1996.
3. H. Hulgaard, S. M. Burns, and G. Borriello. Testing asynchronous circuits: a survey. Integr. VLSI J., 19(3):111-131, 1995.
4. J. B. Khare and W. Maly. From Contamination To Defects, Faults and Yield Loss. Kluwer Academic Publishers, 1996.
5. P. K. Lala. Self-Checking and Fault-Tolerant Digital Design. Morgan Kaufmann Publishers, 2001.
6. A. M. Lines. Pipelined asynchronous circuits. Master's thesis, California Institute of Technology, Pasadena, California, 1996.
7. R. Manohar and A. J. Martin. Quasi-delay-insensitive circuits are Turing complete. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems. IEEE Computer Society Press, 1996.
8. R. Manohar and A. J. Martin. Slack elasticity in concurrent computing. In Proceedings of the Mathematics of Program Construction, pages 272-285. Springer-Verlag, 1998.
9. A. J. Martin. Compiling communicating processes into delay-insensitive vlsi circuits. Distributed Computing, 1:226-234, 1986.
10. A. J. Martin. The limitations to delay-insensitivity in asynchronous circuits. Beauty is our business: a birthday salute to Edsger W. Dijkstra, pages 302-311, 1990.
11. A. J. Martin, A. Lines, R. Manohar, M. Nystroem, P. Penzes, R. Southworth, and U. Cummings. The design of an asynchronous mips r3000 microprocessor. In Proceedings of the 17th Conference on Advanced Research in VLSI(ARVLSI '97), page 164. IEEE Computer Society, 1997.
12. Y. Massoud, S. Majors, J. Kawa, T. Bustami, D. MacMillen, and J. White. Managing on-chip inductive effects. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 10(6):789-797, 2002.
13. V. I. Varshavsky. Circuits insensitive to delays in transistors and wires. Technical report, Helsinki University of Technology, November 1989.
14. A. Yakovlev. Structural technique for fault-masking in asynchronous interfaces. In IEE Proceedings E - Computers and Digital Techniques, pages 81-91. IEEE Computer Society, 1993.