-
1
-
-
3743075441
-
Emulation based real time testing of automotive applications
-
J. Abke, E. Böhl, and C. Henno, "Emulation Based Real Time Testing of Automotive Applications," in 4th IEEE International On-Line Testing Workshop, Capri, Italy, July 6-8, 1998, pp. 28-31.
-
4th IEEE International On-Line Testing Workshop, Capri, Italy, July 6-8, 1998
, pp. 28-31
-
-
Abke, J.1
Böhl, E.2
Henno, C.3
-
2
-
-
84962771693
-
Fault tolerance evaluation using two software based fault injection methods
-
A. Ademaj, P. Grillinger, P. Herout, and J. Hlavicka, "Fault Tolerance Evaluation Using Two Software Based Fault Injection Methods," in 8th IEEE International On-Line Testing Workshop, Isle of Bendor, France, July 8-10, 2002, pp. 21-25.
-
8th IEEE International On-Line Testing Workshop, Isle of Bendor, France, July 8-10, 2002
, pp. 21-25
-
-
Ademaj, A.1
Grillinger, P.2
Herout, P.3
Hlavicka, J.4
-
5
-
-
0034501974
-
Using run-time reconfiguration for fault injection in hardware prototypes
-
IEEE Computer Society Press
-
L. Antoni, R. Leveugle, and B. Fehér, "Using Run-Time Reconfiguration for Fault Injection in Hardware Prototypes," in The IEEE Int. Symposium on Defect and Fault Tolerance in VLSI Systems, Yamanashi, Japan, Oct. 25-27, 2000, IEEE Computer Society Press, 2000, pp. 405-413.
-
(2000)
The IEEE Int. Symposium on Defect and Fault Tolerance in VLSI Systems, Yamanashi, Japan, Oct. 25-27, 2000
, pp. 405-413
-
-
Antoni, L.1
Leveugle, R.2
Fehér, B.3
-
6
-
-
0034501974
-
Using run-time reconfiguration for fault injection in hardware prototypes
-
Los Alamitos, CA: IEEE Computer Society Press
-
L. Antoni, R. Leveugle, and B. Fehér, "Using Run-Time Reconfiguration for Fault Injection in Hardware Prototypes," The 17th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, Vancouver, Canada, Nov. 6-8, 2002, Los Alamitos, CA: IEEE Computer Society Press, 2002, pp. 242-249.
-
(2002)
The 17th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, Vancouver, Canada, Nov. 6-8, 2002
, pp. 242-249
-
-
Antoni, L.1
Leveugle, R.2
Fehér, B.3
-
7
-
-
84893748923
-
New techniques for speeding up fault-injection campaigns
-
L. Berrojo, I. Gonzalez, F. Corno, M. Sonza-Reorda, G. Squillero, L. Entrena, and C. Lopez, "New Techniques for Speeding Up Fault-Injection Campaigns," in Design, Automation and Test in Europe Conference (DATE), March 4-8, 2002, pp. 847-852.
-
Design, Automation and Test in Europe Conference (DATE), March 4-8, 2002
, pp. 847-852
-
-
Berrojo, L.1
Gonzalez, I.2
Corno, F.3
Sonza-Reorda, M.4
Squillero, G.5
Entrena, L.6
Lopez, C.7
-
8
-
-
79960607210
-
Real time effect testing of processor faults
-
E. Böhl, W. Harter, and M. Trunzer, "Real Time Effect Testing of Processor Faults," in 5th IEEE International On-Line Testing Workshop, Rhodes, Greece, July 5-7, 1999, pp. 39-43.
-
5th IEEE International On-Line Testing Workshop, Rhodes, Greece, July 5-7, 1999
, pp. 39-43
-
-
Böhl, E.1
Harter, W.2
Trunzer, M.3
-
9
-
-
27544444307
-
MEFISTO-L: A VHDL-based fault injection tool for the experimental assessment of fault tolerance
-
J. Boué, P. Pétillon, and Y. Crouzet, "MEFISTO-L: A VHDL-Based Fault Injection Tool for the Experimental Assessment of Fault Tolerance," in 28th Symposium on Fault-Tolerant Computing (FTCS), 1998, pp. 168-173.
-
28th Symposium on Fault-Tolerant Computing (FTCS), 1998
, pp. 168-173
-
-
Boué, J.1
Pétillon, P.2
Crouzet, Y.3
-
10
-
-
84962664102
-
Bit-flip injection in processor-based architectures: A case study
-
G.C. Cardarilli, F. Kaddour, A. Leandri, M. Ottavi, S. Pontarelli, and R. Velazco, "Bit-Flip Injection in Processor-Based Architectures: A Case Study," in 8th IEEE International On-Line Testing Workshop, Isle of Bendor, France, July 8-10, 2002, pp. 117-127.
-
8th IEEE International On-Line Testing Workshop, Isle of Bendor, France, July 8-10, 2002
, pp. 117-127
-
-
Cardarilli, G.C.1
Kaddour, F.2
Leandri, A.3
Ottavi, M.4
Pontarelli, S.5
Velazco, R.6
-
11
-
-
0033334585
-
Fault emulation: A new methodology for fault grading
-
K.-T. Cheng, S.-Y. Huang, and W.-J. Dai, "Fault Emulation: A New Methodology for Fault Grading," IEEE Transactions on Computer-Aided Design, vol. 18, no. 10, 1999, pp. 1487-1495.
-
(1999)
IEEE Transactions on Computer-Aided Design
, vol.18
, Issue.10
, pp. 1487-1495
-
-
Cheng, K.-T.1
Huang, S.-Y.2
Dai, W.-J.3
-
12
-
-
84994440156
-
Exploiting FPGA for accelerating fault injection experiments
-
P. Civera, L. Macchiarulo, M. Rebaudengo, M. Sonza Reorda, and M. Violante, "Exploiting FPGA for Accelerating Fault Injection Experiments," in 7th IEEE International On-Line Testing Workshop, Taormina, Italy, July 9-11, 2001, pp. 9-13.
-
7th IEEE International On-Line Testing Workshop, Taormina, Italy, July 9-11, 2001
, pp. 9-13
-
-
Civera, P.1
Macchiarulo, L.2
Rebaudengo, M.3
Sonza Reorda, M.4
Violante, M.5
-
13
-
-
0035193910
-
Exploiting FPGA-based techniques for fault injection campaigns on VLSI circuits
-
Los Alamitos, CA: IEEE Computer Society Press
-
P. Civera, L. Macchiarulo, M. Rebaudengo, M. Sonza Reorda, and A. Violante, "Exploiting FPGA-Based Techniques for Fault Injection Campaigns on VLSI Circuits," in The IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, San Francisco, California, USA, Oct. 24-26, 2001, Los Alamitos, CA: IEEE Computer Society Press, 2001, pp. 250-258.
-
(2001)
The IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, San Francisco, California, USA, Oct. 24-26, 2001
, pp. 250-258
-
-
Civera, P.1
Macchiarulo, L.2
Rebaudengo, M.3
Sonza Reorda, M.4
Violante, A.5
-
14
-
-
0035703565
-
FPGA-based fault injection for microprocessor systems
-
P. Civera, L. Macchiarulo, M. Rebaudengo, M. Sonza Reorda, and A. Violante, "FPGA-Based Fault Injection for Microprocessor Systems," in Asian Test Symposium, Nov. 2001, pp. 304-309.
-
Asian Test Symposium, Nov. 2001
, pp. 304-309
-
-
Civera, P.1
Macchiarulo, L.2
Rebaudengo, M.3
Sonza Reorda, M.4
Violante, A.5
-
15
-
-
0030402886
-
A fault injection technique for VHDL behavioral-level models
-
Winter
-
T.A. Delong, B.W. Johnson, and J.A. Profeta III, "A Fault Injection Technique for VHDL Behavioral-Level Models," IEEE Design & Test of Computers, vol. 13, Winter 1996, pp. 24-33.
-
(1996)
IEEE Design & Test of Computers
, vol.13
, pp. 24-33
-
-
Delong, T.A.1
Johnson, B.W.2
Profeta J.A. III3
-
16
-
-
84947295186
-
A CAD framework foe efficient self-checking data path design
-
R.O. Duarte, I. Alzaher Noufal, and M. Nicolaidis, "A CAD Framework Foe Efficient Self-Checking Data Path Design," in 3rd IEEE Int. On-Line Testing Workshop, Aghia Pelaghia headland, Crete, Greece, July 7-9, 1997, pp. 28-35.
-
3rd IEEE Int. On-Line Testing Workshop, Aghia Pelaghia Headland, Crete, Greece, July 7-9, 1997
, pp. 28-35
-
-
Duarte, R.O.1
Alzaher Noufal, I.2
Nicolaidis, M.3
-
18
-
-
0035202381
-
Comparison and application of different VHDL-based fault injection techniques
-
IEEE Computer Society Press
-
J. Gracia, J.C. Baraza, D. Gil, and P.J. Gil, "Comparison and Application of Different VHDL-Based Fault Injection Techniques," in The IEEE Int. Symposium on Defect and Fault Tolerance in VLSI Systems, San Francisco, California, USA, Oct. 24-26, 2001, IEEE Computer Society Press, 2001, pp. 233-241.
-
(2001)
The IEEE Int. Symposium on Defect and Fault Tolerance in VLSI Systems, San Francisco, California, USA, Oct. 24-26, 2001
, pp. 233-241
-
-
Gracia, J.1
Baraza, J.C.2
Gil, D.3
Gil, P.J.4
-
19
-
-
0024873086
-
Evaluation of error detection schemes using fault injection by heavy-ion radiation
-
U. Gunneflo, J. Karlsson, and J. Torin, "Evaluation of Error Detection Schemes Using Fault Injection by Heavy-Ion Radiation," in 19th Symposium on Fault-Tolerant Computing (FTCS), 1989, pp. 340-347.
-
19th Symposium on Fault-Tolerant Computing (FTCS), 1989
, pp. 340-347
-
-
Gunneflo, U.1
Karlsson, J.2
Torin, J.3
-
20
-
-
0028018774
-
Fault injection into VHDL models: The MEFISTO tool
-
E. Jenn, J. Arlat, M. Rimen, J. Ohlsson, and J. Karlsson, "Fault Injection into VHDL Models: The MEFISTO Tool," in 24th Symposium on Fault-Tolerant Computing (FTCS), 1994, pp. 66-75.
-
24th Symposium on Fault-Tolerant Computing (FTCS), 1994
, pp. 66-75
-
-
Jenn, E.1
Arlat, J.2
Rimen, M.3
Ohlsson, J.4
Karlsson, J.5
-
21
-
-
85064759317
-
FERRARI: A tool for the validation of system dependability properties
-
G.A. Kanawati, N.A. Kanawati, and J.A. Abraham, "FERRARI: A Tool for the Validation of System Dependability Properties," in 22nd Symposium on Fault-Tolerant Computing (FTCS), 1992, pp. 336-344.
-
22nd Symposium on Fault-Tolerant Computing (FTCS), 1992
, pp. 336-344
-
-
Kanawati, G.A.1
Kanawati, N.A.2
Abraham, J.A.3
-
22
-
-
0026709992
-
Two fault injection techniques for test of fault handling mechanisms
-
J. Karlsson, U. Gunneflo, P. Líden, and J. Torin, "Two Fault Injection Techniques for Test of Fault Handling Mechanisms," in International Test Conference (ITC), 1991, pp. 140-149.
-
International Test Conference (ITC), 1991
, pp. 140-149
-
-
Karlsson, J.1
Gunneflo, U.2
Líden, P.3
Torin, J.4
-
23
-
-
79960587920
-
Behavior modeling of faulty complex VLSIs: Why and how?
-
R. Leveugle, "Behavior Modeling of Faulty Complex VLSIs: Why and How?," in The Baltic Electronics Conference, Tallin, Estonia, Oct. 7-9, 1998, pp. 191-194.
-
The Baltic Electronics Conference, Tallin, Estonia, Oct. 7-9, 1998
, pp. 191-194
-
-
Leveugle, R.1
-
24
-
-
33847172128
-
Towards modeling for dependability of complex integrated circuits
-
R. Leveugle, "Towards Modeling for Dependability of Complex Integrated Circuits," in 5th IEEE Int. On-Line Testing Workshop, Rhodes, Greece, July 5-7, 1999, pp. 194-198.
-
5th IEEE Int. On-Line Testing Workshop, Rhodes, Greece, July 5-7, 1999
, pp. 194-198
-
-
Leveugle, R.1
-
25
-
-
0034517345
-
Fault injection in VHDL descriptions and emulation
-
Los Alamitos, CA: IEEE Computer Society Press
-
R. Leveugle, "Fault Injection in VHDL Descriptions and Emulation," in The IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, Yamanashi, Japan, Oct. 25-27, 2000, Los Alamitos, CA: IEEE Computer Society Press, 2000, pp. 414-419.
-
(2000)
The IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, Yamanashi, Japan, Oct. 25-27, 2000
, pp. 414-419
-
-
Leveugle, R.1
-
26
-
-
0035202382
-
A low-cost hardware approach to dependability validation of IPs
-
Los Alamitos, CA: IEEE Computer Society Press
-
R. Leveugle, "A Low-Cost Hardware Approach to Dependability Validation of IPs," in The IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, San Francisco, California, USA, Oct. 24-26, 2001, Los Alamitos, CA: IEEE Computer Society Press, 2001, pp. 242-249.
-
(2001)
The IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, San Francisco, California, USA, Oct. 24-26, 2001
, pp. 242-249
-
-
Leveugle, R.1
-
27
-
-
3042687586
-
Automatic modifications of high level VHDL descriptions for fault detection or tolerance
-
R. Leveugle, "Automatic Modifications of High Level VHDL Descriptions for Fault Detection or Tolerance," in Design, Automation and Test in Europe Conference (DATE), March 4-8, 2002, pp. 837-841.
-
Design, Automation and Test in Europe Conference (DATE), March 4-8, 2002
, pp. 837-841
-
-
Leveugle, R.1
-
28
-
-
0344794518
-
Optimized generation of VHDL mutants for injection of transition errors
-
R. Leveugle and K. Hadjiat, "Optimized Generation of VHDL Mutants for Injection of Transition Errors," in 13th Symposium on Integrated Circuits and Systems Design (SBCC12000), Manaus, Brazil, Sept. 18-24, 2000, pp. 243-248.
-
13th Symposium on Integrated Circuits and Systems Design (SBCC12000), Manaus, Brazil, Sept. 18-24, 2000
, pp. 243-248
-
-
Leveugle, R.1
Hadjiat, K.2
-
29
-
-
84949244684
-
Fault tolerant insertion and verification: A case study
-
A. Manzone and D. De Constantini, "Fault Tolerant Insertion and Verification: A Case Study," in 8th IEEE International On-Line Testing Workshop, Isle of Bendor, France, July 8-10, 2002, pp. 238-242.
-
8th IEEE International On-Line Testing Workshop, Isle of Bendor, France, July 8-10, 2002
, pp. 238-242
-
-
Manzone, A.1
De Constantini, D.2
-
30
-
-
0027962097
-
Taking advantage of ASICs to improve dependability with very low overheads
-
T. Michel, R. Leveugle, G. Saucier, R. Doucet, and P. Chapier, "Taking Advantage of ASICs to Improve Dependability with Very Low Overheads," in ED&TC, 1994, pp. 14-18.
-
(1994)
ED&TC
, pp. 14-18
-
-
Michel, T.1
Leveugle, R.2
Saucier, G.3
Doucet, R.4
Chapier, P.5
-
31
-
-
0002475610
-
New techniques for accelerating fault injection in VHDL descriptions
-
B. Parrotta, M. Rebaudengo, M. Sonza-Reorda, and M. Violante, "New Techniques for Accelerating Fault Injection in VHDL Descriptions," in 6th IEEE Int. On-Line Testing Workshop, Palma de Mallorca, Spain, July 3-5, 2000, pp. 61-66.
-
6th IEEE Int. On-Line Testing Workshop, Palma de Mallorca, Spain, July 3-5, 2000
, pp. 61-66
-
-
Parrotta, B.1
Rebaudengo, M.2
Sonza-Reorda, M.3
Violante, M.4
-
32
-
-
0031353224
-
Validating fault tolerance designs using laser fault injection
-
Los Alamitos, CA: IEEE Computer Society Press
-
J.R. Samson, W. Moreno, and F. Falquez, "Validating Fault Tolerance Designs Using Laser Fault Injection," in The IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, Paris, France, Oct. 20-22, 1997, Los Alamitos, CA: IEEE Computer Society Press, 1997, pp. 175-183.
-
(1997)
The IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, Paris, France, Oct. 20-22, 1997
, pp. 175-183
-
-
Samson, J.R.1
Moreno, W.2
Falquez, F.3
-
33
-
-
0003706707
-
Dependability evaluation of the THOR microprocessor using simulation-based fault injection
-
Technical Report No. 295, Chalmers University of Technology, Department of Computer Engineering, Sweden, November
-
S. Svensson and J. Karlsson, "Dependability Evaluation of the THOR Microprocessor Using Simulation-Based Fault Injection," Technical Report No. 295, Chalmers University of Technology, Department of Computer Engineering, Sweden, November, 1997.
-
(1997)
-
-
Svensson, S.1
Karlsson, J.2
-
34
-
-
0031177081
-
Logic synthesis of multilevel circuits with concurrent error detection
-
July
-
N.A. Touba and E.J. McClusley, "Logic Synthesis of Multilevel Circuits with Concurrent Error Detection," IEEE Transactions on Computer-Aided Design, vol. 16, no. 7, July 1997, pp. 783-789.
-
(1997)
IEEE Transactions on Computer-Aided Design
, vol.16
, Issue.7
, pp. 783-789
-
-
Touba, N.A.1
McClusley, E.J.2
-
35
-
-
0142206123
-
Estimating circuit fault-tolerance by means of transient-fault injection in VHDL
-
F. Vargas, A. Amory, and R. Velazco, "Estimating Circuit Fault-Tolerance by Means of Transient-Fault Injection in VHDL," in 6th IEEE International On-Line Testing Workshop, Palma de Mallorca, Spain, July 3-5, 2000, pp. 67-72.
-
6th IEEE International On-Line Testing Workshop, Palma de Mallorca, Spain, July 3-5, 2000
, pp. 67-72
-
-
Vargas, F.1
Amory, A.2
Velazco, R.3
-
36
-
-
0035193945
-
Upset-like fault injection in VHDL descriptions: A method and preliminary results
-
Los Alamitos, CA: IEEE Computer Society Press
-
R. Velazco, R. Leveugle, and O. Calvo, "Upset-Like Fault Injection in VHDL Descriptions: A Method and Preliminary Results," in The IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, San Francisco, California, USA, Oct. 24-26, 2001, Los Alamitos, CA: IEEE Computer Society Press, 2001, pp. 259-267.
-
(2001)
The IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, San Francisco, California, USA, Oct. 24-26, 2001
, pp. 259-267
-
-
Velazco, R.1
Leveugle, R.2
Calvo, O.3
-
37
-
-
0029546819
-
Emulating static faults using a xilinx based emulator
-
R.W. Wieler, Z. Zhang, and R.D. McLeod, "Emulating Static Faults Using a Xilinx Based Emulator," in IEEE Symp. FPGAs for Custom Computing Machines, Feb. 1995, pp. 110-115.
-
IEEE Symp. FPGAs for Custom Computing Machines, Feb. 1995
, pp. 110-115
-
-
Wieler, R.W.1
Zhang, Z.2
McLeod, R.D.3
|