Asynchronous circuits sensitivity to fault injection

Proceedings - 10th IEEE International On-Line Testing Symposium, IOLTS 2004

Volumn , Issue , 2004, Pages 121-126

  Monnet, Y ^a   Renaudin, M ^a   Leveugle, R ^a  

^a TIMA LABORATORY   (France)

Author keywords

[No Author keywords available]

Indexed keywords

ASYNCHRONOUS CIRCUITS; FAULT INJECTION; SINGLE EVENT TRANSIENT (SET); SINGLE EVENT UPSET (SEU);

ADDERS; BOOLEAN ALGEBRA; COMPUTER AIDED DESIGN; ERROR ANALYSIS; LOGIC GATES; PERTURBATION TECHNIQUES; PUBLIC KEY CRYPTOGRAPHY; SENSITIVITY ANALYSIS; SEQUENTIAL CIRCUITS;

INTEGRATED CIRCUITS;

EID: 10444232677     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/OLT.2004.1319669     Document Type: Conference Paper

References (12)

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