Duplication-based concurrent error detection in asynchronous circuits: Shortcomings and remedies

Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

Volumn 2002-January, Issue , 2002, Pages 345-353

  Verdel, T ^a   Makris, Y ^a  

^a Yale University   (United States)

Author keywords

Asynchronous circuits; Circuit faults; Circuit testing; Clocks; Design automation; Electrical fault detection; Fault detection; Logic circuits; Monitoring; Synchronization

Indexed keywords

ASYNCHRONOUS SEQUENTIAL LOGIC; CLOCKS; COMPUTER AIDED DESIGN; CONVOLUTIONAL CODES; DEFECTS; DESIGN FOR TESTABILITY; ELECTRIC FAULT LOCATION; ERROR DETECTION; ERRORS; FAULT DETECTION; FAULT TOLERANCE; LOGIC DESIGN; MONITORING; SYNCHRONIZATION; VLSI CIRCUITS;

ASYNCHRONOUS CIRCUITS; CIRCUIT FAULTS; CIRCUIT TESTING; DESIGN AUTOMATIONS; ELECTRICAL FAULT DETECTIONS;

LOGIC CIRCUITS;

EID: 33745493023     PISSN: 15505774     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DFTVS.2002.1173531     Document Type: Conference Paper

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