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Volumn 2327 LNCS, Issue , 2002, Pages 133-145

A comprehensive analysis of indirect branch prediction

Author keywords

Branch prediction; Branch Target Buffer; Indirect branch; Microarchitecture; Multi Stage Cascaded Predictor

Indexed keywords

BRANCH PREDICTION; BRANCH TARGET BUFFER; INDIRECT BRANCH; MICROARCHITECTURE; MULTI-STAGE CASCADED PREDICTOR; BRANCH TARGET BUFFERS; MICRO ARCHITECTURES; MULTI STAGE;

EID: 68749090878     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/3-540-47847-7_13     Document Type: Conference Paper
Times cited : (5)

References (16)
  • 5
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    • 0026156263 scopus 로고
    • Branch history table prediction of moving target branches due to subroutine returns
    • D. Kaeli and P. Emma. Branch history table prediction of moving target branches due to subroutine returns. 18th Intl. Symp. on Computer Architecture, 1991.
    • (1991) 18th Intl. Symp. on Computer Architecture
    • Kaeli, D.1    Emma, P.2
  • 8
    • 0021204160 scopus 로고
    • Branch prediction strategies and branch target buffer design
    • J. Lee and A. Smith. Branch prediction strategies and branch target buffer design. IEEE Computer Magazine, 17(1), 1984.
    • (1984) IEEE Computer Magazine , vol.17 , Issue.1
    • Lee, J.1    Smith, A.2
  • 9
    • 68749121842 scopus 로고    scopus 로고
    • S. McFarling Combining branch predictors. Digital Equipment Corporation, WRL Technical Note TN-36, 1993.
    • S. McFarling Combining branch predictors. Digital Equipment Corporation, WRL Technical Note TN-36, 1993.
  • 13
    • 84869709266 scopus 로고    scopus 로고
    • Departamento de Arquitectura de Computadores, UPC, Technical Report DAC-UPC-2001-24
    • O. J. Santana, A. Falcón, E. Fernández, P. Medina, A. Ramírez and M. Valero. Analysis and evaluation of the Multi-Stage Cascaded Predictor. Departamento de Arquitectura de Computadores, UPC, Technical Report DAC-UPC-2001-24, 2001.
    • (2001)
    • Santana, O.J.1    Falcón, A.2    Fernández, E.3    Medina, P.4    Ramírez, A.5    Valero, M.6
  • 16
    • 68749085390 scopus 로고
    • A comprehensive instruction fetch mechanism for a processor supporting speculative execution
    • T. Y. Yeh and Y. Patt. A comprehensive instruction fetch mechanism for a processor supporting speculative execution. 25th Intl. Symp. on Microarchitecture, 1995
    • (1995) 25th Intl. Symp. on Microarchitecture
    • Yeh, T.Y.1    Patt, Y.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.