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Volumn 53, Issue 5, 2006, Pages 1276-1279

Device enhancement using process-strained-Si for sub-100-nm nMOSFET

Author keywords

Contact etch stop layer; Mobility; Strain; Sub 100 nm nMOSFET

Indexed keywords

ELECTRIC CURRENTS; GATES (TRANSISTOR); OSCILLATORS (ELECTRONIC); SEMICONDUCTING SILICON; STRAIN; TRANSCONDUCTANCE;

EID: 33646072803     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2006.871874     Document Type: Article
Times cited : (1)

References (12)
  • 1
    • 0022027064 scopus 로고
    • "Design tradeoffs between surface and buried-channel FET's"
    • Mar
    • G. J. Hu and R. H. Bruce, "Design tradeoffs between surface and buried-channel FET's," IEEE Trans. Electron Devices, vol. ED-32, no. 3, pp. 584-588, Mar. 1985.
    • (1985) IEEE Trans. Electron Devices , vol.ED-32 , Issue.3 , pp. 584-588
    • Hu, G.J.1    Bruce, R.H.2
  • 3
    • 0036923578 scopus 로고    scopus 로고
    • "Novel SOI wafer engineering using low stress and high mobility CMOSFET with (100)-channel for enhanced RF/analog applications"
    • T. Matsumoto, S. Maeda, H. Dang, T. Uchida, K. Ota, and Y. Hirano et al., "Novel SOI wafer engineering using low stress and high mobility CMOSFET with (100)-channel for enhanced RF/analog applications," in IEDM Tech. Dig., 2002, pp. 663-666.
    • (2002) IEDM Tech. Dig. , pp. 663-666
    • Matsumoto, T.1    Maeda, S.2    Dang, H.3    Uchida, T.4    Ota, K.5    Hirano, Y.6
  • 4
    • 0842288292 scopus 로고    scopus 로고
    • "Process-strained Si(PSS) CMOS technology featuring 3D strain engineering"
    • C. H. Ge, C. C. Lin, C. H. Ko, and C. C. Huang et al., "Process-strained Si(PSS) CMOS technology featuring 3D strain engineering," in IEDM Tech. Dig., 2003, pp. 73-76.
    • (2003) IEDM Tech. Dig. , pp. 73-76
    • Ge, C.H.1    Lin, C.C.2    Ko, C.H.3    Huang, C.C.4
  • 5
    • 0036932273 scopus 로고    scopus 로고
    • "Accurate modeling of trench isolation inducted mechanical stress effects on MOSFET electrical performance"
    • R. A. Bianchi, G. Bouche, and O. Roux-dit-Buisson, "Accurate modeling of trench isolation inducted mechanical stress effects on MOSFET electrical performance," in IEDM Tech. Dig., 2002, pp. 117-120.
    • (2002) IEDM Tech. Dig. , pp. 117-120
    • Bianchi, R.A.1    Bouche, G.2    Roux-dit-Buisson, O.3
  • 6
    • 0035696860 scopus 로고    scopus 로고
    • "Investigating the relationship between electron mobility and velocity in deeply scaled NMOS via mechanical stress"
    • Dec
    • A. Locheefeld and D. A. Antoniadis, "Investigating the relationship between electron mobility and velocity in deeply scaled NMOS via mechanical stress," IEEE Electron Device Lett., vol. 22, no. 12, pp. 591-593, Dec. 2001.
    • (2001) IEEE Electron Device Lett. , vol.22 , Issue.12 , pp. 591-593
    • Locheefeld, A.1    Antoniadis, D.A.2
  • 7
    • 24444465420 scopus 로고    scopus 로고
    • "Mechanical stress effect of etch-stop nitride an its impact on deep submicron transistor design"
    • S. Ito et al., "Mechanical stress effect of etch-stop nitride an its impact on deep submicron transistor design," in IEDM Tech. Dig., 2001, pp. 247-250.
    • (2001) IEDM Tech. Dig. , pp. 247-250
    • Ito, S.1
  • 9
    • 0035715857 scopus 로고    scopus 로고
    • "Local mechanical-stress control (LMC): A new technique for CMOS-performance enhancement"
    • A. Shimizu, K. Hachimine, N. Ohki, and M. Kouguchi et al., "Local mechanical-stress control (LMC): A new technique for CMOS-performance enhancement," in IEDM Tech. Dig., 2001, pp. 433-436.
    • (2001) IEDM Tech. Dig. , pp. 433-436
    • Shimizu, A.1    Hachimine, K.2    Ohki, N.3    Kouguchi, M.4
  • 10
    • 0036047592 scopus 로고    scopus 로고
    • "(100) channel strained-SiGe p-MOSFET with enhanced hole mobility and low parasitic resistance"
    • M. Shima, T. Ueno, T. Kumise, H. Shido, Y. Sakuma, and A. Nakamura, "(100) channel strained-SiGe p-MOSFET with enhanced hole mobility and low parasitic resistance," in IEDM Tech. Dig., 2002, pp. 94-95.
    • (2002) IEDM Tech. Dig. , pp. 94-95
    • Shima, M.1    Ueno, T.2    Kumise, T.3    Shido, H.4    Sakuma, Y.5    Nakamura, A.6
  • 11
    • 0032254846 scopus 로고    scopus 로고
    • "Transconductance enhancement in deep submicron strained-Si n-MOSFETs"
    • K. Rim, J. L. Hoyt, and J. F. Gibbons, "Transconductance enhancement in deep submicron strained-Si n-MOSFETs," in IEDM Tech.Dig., 1998, pp. 707-710.
    • (1998) IEDM Tech.Dig. , pp. 707-710
    • Rim, K.1    Hoyt, J.L.2    Gibbons, J.F.3
  • 12
    • 0034227743 scopus 로고    scopus 로고
    • "Fabrication and analysis of deep submicron strained-Si n-MOSFET's"
    • Jul
    • K. Rim, J. L. Hoyt, and J. F. Gibbons, "Fabrication and analysis of deep submicron strained-Si n-MOSFET's," IEEE Trans. Electron Devices, vol. 47, no. 7, pp. 1406-1415, Jul. 2000.
    • (2000) IEEE Trans. Electron Devices , vol.47 , Issue.7 , pp. 1406-1415
    • Rim, K.1    Hoyt, J.L.2    Gibbons, J.F.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.