-
1
-
-
0002927078
-
"High Speed: Not the Only Way to Exploit the Intrinsic Computational Power of Silicon"
-
Digest of Technical Papers
-
T.A.C.M. Claasen, "High Speed: Not the Only Way to Exploit the Intrinsic Computational Power of Silicon," Proc. IEEE Int'l Solid-State Circuits Conf. (ISSCC 1999), Digest of Technical Papers, pp. 22-25, 1999.
-
(1999)
Proc. IEEE Int'l Solid-State Circuits Conf. (ISSCC 1999)
, pp. 22-25
-
-
Claasen, T.A.C.M.1
-
3
-
-
0027311335
-
"Efficient Flow-Sensitive Inter-Procedural Computation of Pointer-Induced Aliases and Side Effects"
-
J. Choi, M. Burke, and P. Carini, "Efficient Flow-Sensitive Inter-Procedural Computation of Pointer-Induced Aliases and Side Effects," Proc. 20th Ann. ACM Symp. Principles of Programming Languages, pp. 233-245, 1993.
-
(1993)
Proc. 20th Ann. ACM Symp. Principles of Programming Languages
, pp. 233-245
-
-
Choi, J.1
Burke, M.2
Carini, P.3
-
4
-
-
0037912292
-
"System Synthesis for Multiprocessor Embedded Applications"
-
L. Carro, M. Kreutz, F.R. Wagner, and M. Oyamada, "System Synthesis for Multiprocessor Embedded Applications," Proc. Design, Automation and Test in Europe Conf. and Exhibition, pp. 697-702, 2000.
-
(2000)
Proc. Design, Automation and Test in Europe Conf. and Exhibition
, pp. 697-702
-
-
Carro, L.1
Kreutz, M.2
Wagner, F.R.3
Oyamada, M.4
-
5
-
-
0034314478
-
"Heterogeneous Multiprocessor for the Management of Real-Time Video and Graphics Streams"
-
Nov
-
M.T.J. Strik, A.H. Timmer, J.L. Van Meerbergen, and G. VanRootselaar, "Heterogeneous Multiprocessor for the Management of Real-Time Video and Graphics Streams," IEEE J. Solid-State Circuits, vol. 35, no. 11, pp. 1722-1731, Nov. 2000.
-
(2000)
IEEE J. Solid-State Circuits
, vol.35
, Issue.11
, pp. 1722-1731
-
-
Strik, M.T.J.1
Timmer, A.H.2
Van Meerbergen, J.L.3
VanRootselaar, G.4
-
6
-
-
0034500770
-
"A Single-Chip Video Signal Processing System with Embedded DRAM"
-
J. Hilgenstock, K. Herrmann, S. Moch, and P. Pirsch, "A Single-Chip Video Signal Processing System with Embedded DRAM," Proc. IEEE Workshop Signal Processing Systems (SiPS 2000), pp. 23-32, 2000.
-
(2000)
Proc. IEEE Workshop Signal Processing Systems (SiPS 2000)
, pp. 23-32
-
-
Hilgenstock, J.1
Herrmann, K.2
Moch, S.3
Pirsch, P.4
-
7
-
-
0033096723
-
"COSYN: Hardware-Software Co-Synthesis of Heterogeneous Distributed Embedded Systems"
-
Mar
-
B.P. Dave, G. Lakshminarayana, and N.K. Jha, "COSYN: Hardware-Software Co-Synthesis of Heterogeneous Distributed Embedded Systems," IEEE Trans. Very Large Scale Integrated Systems, vol. 7, no. 1, pp. 92-104, Mar. 1999.
-
(1999)
IEEE Trans. Very Large Scale Integrated Systems
, vol.7
, Issue.1
, pp. 92-104
-
-
Dave, B.P.1
Lakshminarayana, G.2
Jha, N.K.3
-
8
-
-
0032183521
-
"COHRA: Hardware-Software Cosynthesis of Hierarchical Heterogeneous Distributed Embedded Systems"
-
Oct
-
B.P. Dave and N.K. Jha, "COHRA: Hardware-Software Cosynthesis of Hierarchical Heterogeneous Distributed Embedded Systems," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 17, no. 10, pp. 900-919, Oct. 1998.
-
(1998)
IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems
, vol.17
, Issue.10
, pp. 900-919
-
-
Dave, B.P.1
Jha, N.K.2
-
9
-
-
33746952413
-
"CMAPS: A Cosynthesis Methodology for Application-Oriented General-Purpose Parallel Systems"
-
Jan
-
P.A. Hsiung, "CMAPS: A Cosynthesis Methodology for Application-Oriented General-Purpose Parallel Systems," ACM Trans. Design Automation of Electronic Systems, vol. 5, no. 1, pp. 58-81, Jan. 2000.
-
(2000)
ACM Trans. Design Automation of Electronic Systems
, vol.5
, Issue.1
, pp. 58-81
-
-
Hsiung, P.A.1
-
11
-
-
0005479027
-
"System-Level Co-Design of Heterogeneous Multiprocessor Embedded Systems"
-
PhD thesis, DEI, Politecnico di Milano
-
L. Pomante, "System-Level Co-Design of Heterogeneous Multiprocessor Embedded Systems," PhD thesis, DEI, Politecnico di Milano, 2002.
-
(2002)
-
-
Pomante, L.1
-
12
-
-
0036045883
-
"Metrics for Design Space Exploration of Heterogeneous Multiprocessor Embedded Systems"
-
May
-
L. Pomante, W. Fornaciari, D. Sciuto, and F. Salice, "Metrics for Design Space Exploration of Heterogeneous Multiprocessor Embedded Systems," IEEE Proc. 10th Workshop Hardware/Software Codesign, May 2002.
-
(2002)
IEEE Proc. 10th Workshop Hardware/Software Codesign
-
-
Pomante, L.1
Fornaciari, W.2
Sciuto, D.3
Salice, F.4
-
15
-
-
0030651962
-
"Data-Flow Assisted Behavioral Partitioning for Embedded Systems"
-
S. Agrawal and R.K. Gupta, "Data-Flow Assisted Behavioral Partitioning for Embedded Systems," IEEE Proc. 34th Design Automation Conf., pp. 709-712, 1997.
-
(1997)
IEEE Proc. 34th Design Automation Conf.
, pp. 709-712
-
-
Agrawal, S.1
Gupta, R.K.2
-
17
-
-
0034226675
-
"Codex-dp: Co-Design of Communicating Systems Using Dynamic Programming"
-
July
-
J.M. Chang and M. Pedram, "Codex-dp: Co-Design of Communicating Systems Using Dynamic Programming," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 19, no. 7, pp. 732-744, July 2000.
-
(2000)
IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems
, vol.19
, Issue.7
, pp. 732-744
-
-
Chang, J.M.1
Pedram, M.2
-
18
-
-
0030684242
-
"Functional Partitioning for Hardware-Software Codesign Using Genetic Algorithms"
-
J.I. Hidalgo and J. Lanchares, "Functional Partitioning for Hardware-Software Codesign Using Genetic Algorithms," Proc. 23rd EUROMICRO Conf., pp. 631-638, 1997.
-
(1997)
Proc. 23rd EUROMICRO Conf.
, pp. 631-638
-
-
Hidalgo, J.I.1
Lanchares, J.2
-
20
-
-
84974687699
-
"Scheduling Algorithms for Multiprogramming in a Hard Real-Time Environment"
-
C.L. Liu and J.W. Layland, "Scheduling Algorithms for Multiprogramming in a Hard Real-Time Environment," J. ACM, vol. 20, no. 1, pp. 37-53, 1973.
-
(1973)
J. ACM
, vol.20
, Issue.1
, pp. 37-53
-
-
Liu, C.L.1
Layland, J.W.2
-
22
-
-
33645836508
-
-
GALIB
-
GALIB, http://lancet.mit.edu/ga/, 1999.
-
(1999)
-
-
-
23
-
-
0008877249
-
"Embedded Ultra Low Power Intel 486T GX Processor Datasheet"
-
Intel
-
Intel, "Embedded Ultra Low Power Intel 486T GX Processor Datasheet," http://developer.intel.com/design/intarch/DATASHTS/272755.htm, 2002..
-
(2002)
-
-
-
24
-
-
0005425907
-
"Taming the SHARC"
-
technical report, Ixthos Inc
-
T. Cooper, "Taming the SHARC," technical report, Ixthos Inc., 2000.
-
(2000)
-
-
Cooper, T.1
-
26
-
-
0003849991
-
"Reconfigurable Architectures for General-Purpose Computing"
-
Technical Report No. 1586, MIT-AI Laboratory
-
A. DeHon, "Reconfigurable Architectures for General-Purpose Computing," Technical Report No. 1586, MIT-AI Laboratory, 1996.
-
(1996)
-
-
DeHon, A.1
-
27
-
-
0028737506
-
"System-Level Design Guidance Using Algorithm Properties"
-
L. Guerra, M. Potkonjak, and M. Rabaey, "System-Level Design Guidance Using Algorithm Properties," J. VLSI Signal Processing, vol. VII, pp. 73-82, 1994.
-
(1994)
J. VLSI Signal Processing
, vol.7
, pp. 73-82
-
-
Guerra, L.1
Potkonjak, M.2
Rabaey, M.3
-
28
-
-
0028581812
-
"A Global Criticality/Local Phase Driven Algorithm for the Constrained Hardware/Software Partitioning Problem"
-
A. Kavalade and A. Lee, "A Global Criticality/Local Phase Driven Algorithm for the Constrained Hardware/Software Partitioning Problem," Proc. IEEE CODES/CASHE, pp. 42-48, 1994.
-
(1994)
Proc. IEEE CODES/CASHE
, pp. 42-48
-
-
Kavalade, A.1
Lee, A.2
-
29
-
-
0026865713
-
"GENOA: A Customizable, Language- and Front-End Independent Code Analyzer"
-
P. Devanbu, "GENOA: A Customizable, Language- and Front-End Independent Code Analyzer," Proc. Int'l Conf. Software Eng. (ICSE), 1992.
-
(1992)
Proc. Int'l Conf. Software Eng. (ICSE)
-
-
Devanbu, P.1
-
30
-
-
33645835930
-
-
http://www.systemc.org, 2006.
-
(2006)
-
-
-
31
-
-
0034262613
-
"Compiler Analysis for Cache Coherence: Interprocedural Array Data-Flow Analysis and Its Impact on Cache Performance"
-
Sept
-
L. Choi and P.-C. Yew, "Compiler Analysis for Cache Coherence: Interprocedural Array Data-Flow Analysis and Its Impact on Cache Performance," IEEE Trans. Parallel and Distributed Systems, vol. 11, no. 9, pp. 879-896, Sept. 2000.
-
(2000)
IEEE Trans. Parallel and Distributed Systems
, vol.11
, Issue.9
, pp. 879-896
-
-
Choi, L.1
Yew, P.-C.2
-
32
-
-
33645804012
-
"An Internal Representation Model for System-Level Co-Design of Heterogeneous Multiprocessor Embedded System"
-
Sept
-
F. Salice, W. Fornaciari, L. Pomante, and D. Sciuto, "An Internal Representation Model for System-Level Co-Design of Heterogeneous Multiprocessor Embedded System," Proc. Forum Specification and Design Languages, pp. 669-679, Sept. 2003.
-
(2003)
Proc. Forum Specification and Design Languages
, pp. 669-679
-
-
Salice, F.1
Fornaciari, W.2
Pomante, L.3
Sciuto, D.4
-
33
-
-
33645826926
-
-
http://www.synopsys.com, 2006.
-
(2006)
-
-
-
34
-
-
0037998933
-
"Partitioning of Embedded Applications onto Heterogeneous Multiprocessor Architectures"
-
Mar
-
L. DelVecchio, W. Fornaciari, L. Pomante, and F. Salice, "Partitioning of Embedded Applications onto Heterogeneous Multiprocessor Architectures," Proc. ACM Symp. Applied Computing, pp. 661-665, Mar. 2003.
-
(2003)
Proc. ACM Symp. Applied Computing
, pp. 661-665
-
-
DelVecchio, L.1
Fornaciari, W.2
Pomante, L.3
Salice, F.4
-
35
-
-
33645822099
-
-
http://www.tensilica.com, 2006.
-
(2006)
-
-
-
36
-
-
0034854046
-
"Automatic Generation of Application-Specific Architectures for Heterogeneous Multiprocessor System-on-Chip"
-
D. Lyonnard, Y. Sungjoo, A. Baghdadi, and A.A. Jerraya, "Automatic Generation of Application-Specific Architectures for Heterogeneous Multiprocessor System-on-Chip," IEEE Proc. Design Automation Conf., pp. 518-523, 2001.
-
(2001)
IEEE Proc. Design Automation Conf.
, pp. 518-523
-
-
Lyonnard, D.1
Sungjoo, Y.2
Baghdadi, A.3
Jerraya, A.A.4
-
38
-
-
0036708865
-
"Combining a Performance Estimation Methodology with a Hardware/Software Codesign Flow Supporting Multiprocessor Systems"
-
A. Baghdadi, N.E. Zergainoh, W.O. Cesario, and A.A. Jerraya, "Combining a Performance Estimation Methodology with a Hardware/Software Codesign Flow Supporting Multiprocessor Systems," IEEE Trans. Software Eng., vol. 28, no. 9, pp. 822-831, 2002.
-
(2002)
IEEE Trans. Software Eng.
, vol.28
, Issue.9
, pp. 822-831
-
-
Baghdadi, A.1
Zergainoh, N.E.2
Cesario, W.O.3
Jerraya, A.A.4
-
39
-
-
84893658996
-
"An Efficient Architecture Model for Systematic Design of Application-Specific Multiprocessor SoC"
-
A. Baghdadi, D. Lyonnard, N.E. Zergainoh, and A.A. Jerraya, "An Efficient Architecture Model for Systematic Design of Application-Specific Multiprocessor SoC," IEEE Proc. Design, Automation and Test in Europe, pp. 55-62, 2001.
-
(2001)
IEEE Proc. Design, Automation and Test in Europe
, pp. 55-62
-
-
Baghdadi, A.1
Lyonnard, D.2
Zergainoh, N.E.3
Jerraya, A.A.4
-
40
-
-
0034848814
-
"CODEF: A System Level Design Space Exploration Tool"
-
M. Auguin, L. Capella, F. Cuesta, and E. Gresset, "CODEF: A System Level Design Space Exploration Tool," Proc. IEEE Int'l Conf. Acoustics, Speech, and Signal Processing, vol. 2, pp. 1145-1148, 2002.
-
(2002)
Proc. IEEE Int'l Conf. Acoustics, Speech, and Signal Processing
, vol.2
, pp. 1145-1148
-
-
Auguin, M.1
Capella, L.2
Cuesta, F.3
Gresset, E.4
-
41
-
-
0035410693
-
"Hw/Sw Cosimulation for Fast Design Space Exploration of Multiprocessor Embedded Systems"
-
D. Sciuto, F. Salice, W. Fornaciari, and L. Pomante, "Hw/Sw Cosimulation for Fast Design Space Exploration of Multiprocessor Embedded Systems," Canadian J. Electrical and Computer Eng., vol. 26, nos. 3/4, pp. 135-140, 2001.
-
(2001)
Canadian J. Electrical and Computer Eng.
, vol.26
, Issue.3-4
, pp. 135-140
-
-
Sciuto, D.1
Salice, F.2
Fornaciari, W.3
Pomante, L.4
-
42
-
-
33645798627
-
"Sched_PA: A Scheduler in SystemC"
-
master's thesis, Univ. of Illinois at Chicago
-
P. Taddei and A. Tornatore, "Sched_PA: A Scheduler in SystemC," master's thesis, Univ. of Illinois at Chicago, 2003.
-
(2003)
-
-
Taddei, P.1
Tornatore, A.2
-
43
-
-
0036862631
-
"Static Power Modeling of 32-Bit Microprocessors"
-
Nov
-
C. Brandolese, F. Salice, W. Fornaciari, and D. Sciuto, "Static Power Modeling of 32-Bit Microprocessors," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 21, no. 11, pp. 1306-1316, Nov. 2002.
-
(2002)
IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems
, vol.21
, Issue.11
, pp. 1306-1316
-
-
Brandolese, C.1
Salice, F.2
Fornaciari, W.3
Sciuto, D.4
-
44
-
-
0036949020
-
"Modeling Assembly Instruction Timing in Superscalar Architectures"
-
G. Beltrame, C. Brandolese, W. Fornaciari, F. Salice, D. Sciuto, and V. Trianni, "Modeling Assembly Instruction Timing in Superscalar Architectures," Proc. IEEE Int'l Symp. System Synthesis, pp. 132-137, 2002.
-
(2002)
Proc. IEEE Int'l Symp. System Synthesis
, pp. 132-137
-
-
Beltrame, G.1
Brandolese, C.2
Fornaciari, W.3
Salice, F.4
Sciuto, D.5
Trianni, V.6
-
45
-
-
0034785301
-
"Dynamic Modeling of Inter-Instruction Effects for Execution Time Estimation"
-
G. Beltrame, C. Brandolese, W. Fornaciari, F. Salice, D. Sciuto, and V. Trianni, "Dynamic Modeling of Inter-Instruction Effects for Execution Time Estimation," Proc. IEEE Int'l Symp. System Synthesis, pp. 136-141, 2001.
-
(2001)
Proc. IEEE Int'l Symp. System Synthesis
, pp. 136-141
-
-
Beltrame, G.1
Brandolese, C.2
Fornaciari, W.3
Salice, F.4
Sciuto, D.5
Trianni, V.6
-
46
-
-
4444254091
-
"An Area Estimation Methodology for FPGA Based Designs at Systemc-Level"
-
C. Brandolese, W. Fornaciari, and F. Salice, "An Area Estimation Methodology for FPGA Based Designs at Systemc-Level," Proc. IEEE Design Automation Conf., pp. 129-132, 2004.
-
(2004)
Proc. IEEE Design Automation Conf.
, pp. 129-132
-
-
Brandolese, C.1
Fornaciari, W.2
Salice, F.3
|