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Volumn 55, Issue 5, 2006, Pages 508-519

Affinity-driven system design exploration for heterogeneous multiprocessor SoC

Author keywords

Codesign; Embedded systems; Heterogeneous systems; Metrics; Multiprocessor systems; System on Chip

Indexed keywords

COMPUTER ARCHITECTURE; COMPUTER SIMULATION; EMBEDDED SYSTEMS; MICROPROCESSOR CHIPS; SYSTEMS ANALYSIS;

EID: 33645827135     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/TC.2006.66     Document Type: Article
Times cited : (37)

References (46)
  • 1
    • 0002927078 scopus 로고    scopus 로고
    • "High Speed: Not the Only Way to Exploit the Intrinsic Computational Power of Silicon"
    • Digest of Technical Papers
    • T.A.C.M. Claasen, "High Speed: Not the Only Way to Exploit the Intrinsic Computational Power of Silicon," Proc. IEEE Int'l Solid-State Circuits Conf. (ISSCC 1999), Digest of Technical Papers, pp. 22-25, 1999.
    • (1999) Proc. IEEE Int'l Solid-State Circuits Conf. (ISSCC 1999) , pp. 22-25
    • Claasen, T.A.C.M.1
  • 5
    • 0034314478 scopus 로고    scopus 로고
    • "Heterogeneous Multiprocessor for the Management of Real-Time Video and Graphics Streams"
    • Nov
    • M.T.J. Strik, A.H. Timmer, J.L. Van Meerbergen, and G. VanRootselaar, "Heterogeneous Multiprocessor for the Management of Real-Time Video and Graphics Streams," IEEE J. Solid-State Circuits, vol. 35, no. 11, pp. 1722-1731, Nov. 2000.
    • (2000) IEEE J. Solid-State Circuits , vol.35 , Issue.11 , pp. 1722-1731
    • Strik, M.T.J.1    Timmer, A.H.2    Van Meerbergen, J.L.3    VanRootselaar, G.4
  • 7
    • 0033096723 scopus 로고    scopus 로고
    • "COSYN: Hardware-Software Co-Synthesis of Heterogeneous Distributed Embedded Systems"
    • Mar
    • B.P. Dave, G. Lakshminarayana, and N.K. Jha, "COSYN: Hardware-Software Co-Synthesis of Heterogeneous Distributed Embedded Systems," IEEE Trans. Very Large Scale Integrated Systems, vol. 7, no. 1, pp. 92-104, Mar. 1999.
    • (1999) IEEE Trans. Very Large Scale Integrated Systems , vol.7 , Issue.1 , pp. 92-104
    • Dave, B.P.1    Lakshminarayana, G.2    Jha, N.K.3
  • 8
    • 0032183521 scopus 로고    scopus 로고
    • "COHRA: Hardware-Software Cosynthesis of Hierarchical Heterogeneous Distributed Embedded Systems"
    • Oct
    • B.P. Dave and N.K. Jha, "COHRA: Hardware-Software Cosynthesis of Hierarchical Heterogeneous Distributed Embedded Systems," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 17, no. 10, pp. 900-919, Oct. 1998.
    • (1998) IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems , vol.17 , Issue.10 , pp. 900-919
    • Dave, B.P.1    Jha, N.K.2
  • 9
    • 33746952413 scopus 로고    scopus 로고
    • "CMAPS: A Cosynthesis Methodology for Application-Oriented General-Purpose Parallel Systems"
    • Jan
    • P.A. Hsiung, "CMAPS: A Cosynthesis Methodology for Application-Oriented General-Purpose Parallel Systems," ACM Trans. Design Automation of Electronic Systems, vol. 5, no. 1, pp. 58-81, Jan. 2000.
    • (2000) ACM Trans. Design Automation of Electronic Systems , vol.5 , Issue.1 , pp. 58-81
    • Hsiung, P.A.1
  • 11
    • 0005479027 scopus 로고    scopus 로고
    • "System-Level Co-Design of Heterogeneous Multiprocessor Embedded Systems"
    • PhD thesis, DEI, Politecnico di Milano
    • L. Pomante, "System-Level Co-Design of Heterogeneous Multiprocessor Embedded Systems," PhD thesis, DEI, Politecnico di Milano, 2002.
    • (2002)
    • Pomante, L.1
  • 15
    • 0030651962 scopus 로고    scopus 로고
    • "Data-Flow Assisted Behavioral Partitioning for Embedded Systems"
    • S. Agrawal and R.K. Gupta, "Data-Flow Assisted Behavioral Partitioning for Embedded Systems," IEEE Proc. 34th Design Automation Conf., pp. 709-712, 1997.
    • (1997) IEEE Proc. 34th Design Automation Conf. , pp. 709-712
    • Agrawal, S.1    Gupta, R.K.2
  • 18
    • 0030684242 scopus 로고    scopus 로고
    • "Functional Partitioning for Hardware-Software Codesign Using Genetic Algorithms"
    • J.I. Hidalgo and J. Lanchares, "Functional Partitioning for Hardware-Software Codesign Using Genetic Algorithms," Proc. 23rd EUROMICRO Conf., pp. 631-638, 1997.
    • (1997) Proc. 23rd EUROMICRO Conf. , pp. 631-638
    • Hidalgo, J.I.1    Lanchares, J.2
  • 19
  • 20
    • 84974687699 scopus 로고
    • "Scheduling Algorithms for Multiprogramming in a Hard Real-Time Environment"
    • C.L. Liu and J.W. Layland, "Scheduling Algorithms for Multiprogramming in a Hard Real-Time Environment," J. ACM, vol. 20, no. 1, pp. 37-53, 1973.
    • (1973) J. ACM , vol.20 , Issue.1 , pp. 37-53
    • Liu, C.L.1    Layland, J.W.2
  • 22
    • 33645836508 scopus 로고    scopus 로고
    • GALIB
    • GALIB, http://lancet.mit.edu/ga/, 1999.
    • (1999)
  • 23
    • 0008877249 scopus 로고    scopus 로고
    • "Embedded Ultra Low Power Intel 486T GX Processor Datasheet"
    • Intel
    • Intel, "Embedded Ultra Low Power Intel 486T GX Processor Datasheet," http://developer.intel.com/design/intarch/DATASHTS/272755.htm, 2002..
    • (2002)
  • 24
    • 0005425907 scopus 로고    scopus 로고
    • "Taming the SHARC"
    • technical report, Ixthos Inc
    • T. Cooper, "Taming the SHARC," technical report, Ixthos Inc., 2000.
    • (2000)
    • Cooper, T.1
  • 26
    • 0003849991 scopus 로고    scopus 로고
    • "Reconfigurable Architectures for General-Purpose Computing"
    • Technical Report No. 1586, MIT-AI Laboratory
    • A. DeHon, "Reconfigurable Architectures for General-Purpose Computing," Technical Report No. 1586, MIT-AI Laboratory, 1996.
    • (1996)
    • DeHon, A.1
  • 27
    • 0028737506 scopus 로고
    • "System-Level Design Guidance Using Algorithm Properties"
    • L. Guerra, M. Potkonjak, and M. Rabaey, "System-Level Design Guidance Using Algorithm Properties," J. VLSI Signal Processing, vol. VII, pp. 73-82, 1994.
    • (1994) J. VLSI Signal Processing , vol.7 , pp. 73-82
    • Guerra, L.1    Potkonjak, M.2    Rabaey, M.3
  • 28
    • 0028581812 scopus 로고
    • "A Global Criticality/Local Phase Driven Algorithm for the Constrained Hardware/Software Partitioning Problem"
    • A. Kavalade and A. Lee, "A Global Criticality/Local Phase Driven Algorithm for the Constrained Hardware/Software Partitioning Problem," Proc. IEEE CODES/CASHE, pp. 42-48, 1994.
    • (1994) Proc. IEEE CODES/CASHE , pp. 42-48
    • Kavalade, A.1    Lee, A.2
  • 29
    • 0026865713 scopus 로고
    • "GENOA: A Customizable, Language- and Front-End Independent Code Analyzer"
    • P. Devanbu, "GENOA: A Customizable, Language- and Front-End Independent Code Analyzer," Proc. Int'l Conf. Software Eng. (ICSE), 1992.
    • (1992) Proc. Int'l Conf. Software Eng. (ICSE)
    • Devanbu, P.1
  • 30
    • 33645835930 scopus 로고    scopus 로고
    • http://www.systemc.org, 2006.
    • (2006)
  • 31
    • 0034262613 scopus 로고    scopus 로고
    • "Compiler Analysis for Cache Coherence: Interprocedural Array Data-Flow Analysis and Its Impact on Cache Performance"
    • Sept
    • L. Choi and P.-C. Yew, "Compiler Analysis for Cache Coherence: Interprocedural Array Data-Flow Analysis and Its Impact on Cache Performance," IEEE Trans. Parallel and Distributed Systems, vol. 11, no. 9, pp. 879-896, Sept. 2000.
    • (2000) IEEE Trans. Parallel and Distributed Systems , vol.11 , Issue.9 , pp. 879-896
    • Choi, L.1    Yew, P.-C.2
  • 32
    • 33645804012 scopus 로고    scopus 로고
    • "An Internal Representation Model for System-Level Co-Design of Heterogeneous Multiprocessor Embedded System"
    • Sept
    • F. Salice, W. Fornaciari, L. Pomante, and D. Sciuto, "An Internal Representation Model for System-Level Co-Design of Heterogeneous Multiprocessor Embedded System," Proc. Forum Specification and Design Languages, pp. 669-679, Sept. 2003.
    • (2003) Proc. Forum Specification and Design Languages , pp. 669-679
    • Salice, F.1    Fornaciari, W.2    Pomante, L.3    Sciuto, D.4
  • 33
    • 33645826926 scopus 로고    scopus 로고
    • http://www.synopsys.com, 2006.
    • (2006)
  • 34
    • 0037998933 scopus 로고    scopus 로고
    • "Partitioning of Embedded Applications onto Heterogeneous Multiprocessor Architectures"
    • Mar
    • L. DelVecchio, W. Fornaciari, L. Pomante, and F. Salice, "Partitioning of Embedded Applications onto Heterogeneous Multiprocessor Architectures," Proc. ACM Symp. Applied Computing, pp. 661-665, Mar. 2003.
    • (2003) Proc. ACM Symp. Applied Computing , pp. 661-665
    • DelVecchio, L.1    Fornaciari, W.2    Pomante, L.3    Salice, F.4
  • 35
    • 33645822099 scopus 로고    scopus 로고
    • http://www.tensilica.com, 2006.
    • (2006)
  • 36
    • 0034854046 scopus 로고    scopus 로고
    • "Automatic Generation of Application-Specific Architectures for Heterogeneous Multiprocessor System-on-Chip"
    • D. Lyonnard, Y. Sungjoo, A. Baghdadi, and A.A. Jerraya, "Automatic Generation of Application-Specific Architectures for Heterogeneous Multiprocessor System-on-Chip," IEEE Proc. Design Automation Conf., pp. 518-523, 2001.
    • (2001) IEEE Proc. Design Automation Conf. , pp. 518-523
    • Lyonnard, D.1    Sungjoo, Y.2    Baghdadi, A.3    Jerraya, A.A.4
  • 38
    • 0036708865 scopus 로고    scopus 로고
    • "Combining a Performance Estimation Methodology with a Hardware/Software Codesign Flow Supporting Multiprocessor Systems"
    • A. Baghdadi, N.E. Zergainoh, W.O. Cesario, and A.A. Jerraya, "Combining a Performance Estimation Methodology with a Hardware/Software Codesign Flow Supporting Multiprocessor Systems," IEEE Trans. Software Eng., vol. 28, no. 9, pp. 822-831, 2002.
    • (2002) IEEE Trans. Software Eng. , vol.28 , Issue.9 , pp. 822-831
    • Baghdadi, A.1    Zergainoh, N.E.2    Cesario, W.O.3    Jerraya, A.A.4
  • 41
    • 0035410693 scopus 로고    scopus 로고
    • "Hw/Sw Cosimulation for Fast Design Space Exploration of Multiprocessor Embedded Systems"
    • D. Sciuto, F. Salice, W. Fornaciari, and L. Pomante, "Hw/Sw Cosimulation for Fast Design Space Exploration of Multiprocessor Embedded Systems," Canadian J. Electrical and Computer Eng., vol. 26, nos. 3/4, pp. 135-140, 2001.
    • (2001) Canadian J. Electrical and Computer Eng. , vol.26 , Issue.3-4 , pp. 135-140
    • Sciuto, D.1    Salice, F.2    Fornaciari, W.3    Pomante, L.4
  • 42
    • 33645798627 scopus 로고    scopus 로고
    • "Sched_PA: A Scheduler in SystemC"
    • master's thesis, Univ. of Illinois at Chicago
    • P. Taddei and A. Tornatore, "Sched_PA: A Scheduler in SystemC," master's thesis, Univ. of Illinois at Chicago, 2003.
    • (2003)
    • Taddei, P.1    Tornatore, A.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.