Modeling assembly instruction timing in superscalar architectures

Proceedings of the International Symposium on System Synthesis

Volumn , Issue , 2002, Pages 132-137

  Beltrame, G ^b   Brandolese, C ^a   Fornaciari, W ^a   Salice, F ^a   Sciuto, D ^a   Trianni, V ^a  

^a POLITECNICO DI MILANO   (Italy)

^b CEFRIEL   (Italy)

Author keywords

Assembly level analysis; Performance estimation; Superscalar architectures

Indexed keywords

COMPUTER SIMULATION; DATA REDUCTION; EMBEDDED SYSTEMS; MATHEMATICAL MODELS;

ASSEMBLY LEVEL ANALYSIS; COMPUTATIONAL EFFICIENCY; SOFTWARE PROGRAMS; SUPERSCALAR ARCHITECTURES;

REDUCED INSTRUCTION SET COMPUTING;

EID: 0036949020     PISSN: 10801820     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/581199.581230     Document Type: Conference Paper

References (16)

1. G. Beltrame. A Model for Assembly Instruction Timing and Power Estimation on Superscalar Architectures. Technical report, Cefriel Institute, March 2002.
2. G. Beltrame, C. Brandolese, W. Fornaciari, F. Salice, D. Sciuto, and V. Trianni. An assembly-level execution-time model for pipelined architectures. In Proc. of Intnl. Conference on Computer Aided Design, pages 195-200, San Jose, CA, November 2001.
3. C. Brandolese, W. Fornaciari, F. Salice, and D. Sciuto. An instruction-level functionality-based energy estimation model for 32-bits microprocessors. In Proc. of the 36th Design Automation Conference, pages 346-350, 2000.
4. K. Chen, S. Malik, and D. August. Retargetable static timing analysis for embedded software. In Proc. of the 14th International Symposium on System Synthesis, pages 39-44, 2001.
5. T. Conte and C. Gimarc. Fast Simulation of Computer Architectures. Kluwer Academic Publishers, 1995.
6. R. Desikan, D. Burger, and S. W. Keckler. Measuring experimental error in microprocessor simulation. In Proc. of the 28th Intnl. Symposium on Computer Architecture, pages 49-58, 2001.
7. J. Emer. Asim: A performance model framework. Computer, 35(2):68-76, 2002.
8. J. Hennessy and D. A. Patterson. Computer Architecture - A Quantitative Approach. Morgan Kaufmann Publishers, San Mateo, II edition, 1996.
9. A. Hergenhan and W. Rosenstiel. Static timing analysis of embedded software on advanced processor architectures. In Proc. of the Design, Automation and Test in Europe Conference and Exhibition, pages 552-559, 2000.
10. M. Lazarescu, J. Bammi, E. Harcourt, L. Lavagno, and M. Lajolo. Compilation-based software performance estimation for system level design. In Proc. of the 6th Intnl. Workshop on Hardware/Software Codesing, pages 65-69, 1998.
11. J. Liu, M. Lajolo, and A. Sangiovanni-Vincentelli. Software timing analysis using hw/sw cosimulation and instruction set siumulator. In Proc. of the 6th Intnl. Workshop on Hardware/Software Codesing, pages 65-69, 1998.
12. S. Malik, M. Martonosi, and Y.-T. S. Li. Static timing analysis of embedded software. In Proc. of the 33rd Design Automation Conference, pages 147-152, 1997.
13. S. S. Mukherjee, V. S. Adve, T. Austin, J. Emer, and S. P. Magnusson. Performance simulation tools. Computer 35(2), 2002.
14. D. Sima, T. Fountain, and P. Klaksuk. Advanced Computer Architectures - A Design Space Approach. Addison-Wesley, 1998.
15. Sun Microsystems. microSPARC™-Hep source distribution. http://www.sun.com.
16. Sun Microsystems. Prying into processes and workloads. Unix Insider, 4/1/98.