An efficient architecture model for systematic design of application-specific multiprocessor SoC

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2001, Pages 55-62

  Baghdadi, Amer ^a   Lyonnard, Damien ^a   Zergainoh, Nacer E ^a   Jerraya, Ahmed A ^a  

^a TIMA LABORATORY   (France)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION SPECIFIC MULTIPROCESSORS; ARCHITECTURE MODELING; DESIGN PROCESS; EFFICIENT ARCHITECTURE; GENERIC ARCHITECTURE; KEY CHARACTERISTICS; MULTI-PROCESSOR SOC; SYSTEMATIC DESIGNS;

COMPUTER SOFTWARE REUSABILITY; EXHIBITIONS; PRODUCT DESIGN;

AUTOMATION;

EID: 84893658996     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2001.915001     Document Type: Conference Paper

References (34)

1. S. Antoniazzi, A. Balboni, W. Fomaciari, and D. Sciuto, "Hardware/Software codesign for embedded telecom systems", In proceedings of ICCD'94, October 1994.
2. F. Balarin, E. Sentovich, M. Chiodo, P. Giusto, H. Hsieh, B. Tabbara, A. Jurecska, L. Lavagno, C. Passerone, K. Suzuki, and A. Sangiovanni-Vincentelli, "Hardware-Software Codesign of Embedded Systems - The POL1S Approach.", Kluwer Academic Publishers, 1997.
3. R. A. Bergamaschi, and W. R. Lee, "Designing Systems-on-Chip Using Cores", In the 37th Design Automation Conference, June 2000.
4. J-Y. Brunei, W. M. Kruijtzer, H. J. H. N. Renter, F. Pétrot, L. Pasquier, E. A. De Kock, and W. J. M. Smits, "COSY Communication IP's", In the 37th Design Automation Conference, June 2000.
5. P. H. Chou, R. B. Ortega, and G. Bordello, "The Chinook hardware/software co-synthesis system", In the 8th International Symposium on System Synthesis, September 1995.
6. D. Culler and J. P. Singh with A. Gupta, "Parallel Computer Architecture: A Hardware/Software Approach", Morgan Kaufmann Publishers, August 1998.
7. G. H. J. Eikerling, W. Hardt, J. Gerlach, and W. Rosenstiel, "A Methodology for Rapid Analysis and Optimization of Embedded Systems", International IEEE Symposium and Workshop on ECBS, D-Friedrichshafen, March 1996.
8. D. D. Gajski, F. Vahid, and S. Narayan, "A system-design methodology: Executable-specification refinement". In the European Conference on Design Automation, February 1994.
9. M. Genoe, P. Delforge, and E. Schutz, "Experiences of IP Reuse in System-on-Chip Design for ADSL", In the IEEE International Solid-State Circuits Conference, 1999.
10. P. Gerin, S. Yoo, G. Nicolescu, A. A. Jerraya, "Scalable and Flexible Cosimulation of SoC Designs with Heterogeneous Multiprocessor Target Architectures", In the ASP-DAC, 2001.
11. R. K. Gupta, C. Coelho, and G. De Micheli, "Synthesis and simulation of digital systems containing interacting hardware and software components", In the 29th Design Automation Conference, June 1992.
12. G. Koch, U. Weinmann, U. Kebschull, and W. Rosenstiel, "System prototyping in the COBRA project", Journal on Microprocessors and Microsystems, Elsevier, vol. 20, no. 3, May 1996.
13. E. A. De Kock, G. Essink, W. J. M. Smits, P. Van der Wolf, J.- Y. Brunei, W. M. Kruijtzer, P. Lieverse, K. A. Vissers, "YAP1: Application Modeling for Signal Processing Systems", In the 37th Design Automation Conference, June 2000.
14. C. Lennard, P. Schaumont, G. De Jong, A. Haverinen, P. Hardee, "Standards for System-Level Design: Practical Reality or Solution in Search of a Question?", In Design, Automation and Test in Europe Conference, 2000.
15. J. Madsen, J. Grode, P. V. Knudsen, M. E. Petersen and A. Haxthausen, "LYCOS: the Lyngby CoSynthesis System", Design Automation for Embedded Systems, vol. 2, n. 2, 1997.
16. G. De Micheli, "Computer-aided hardware-software codesign", IEEE Micro, 14(4):10-16, August 1994.
17. A. Niemegeers, G. De Jong, M. De Langhe, "Early system covalidation based on a hierarchical specification flow", In the IEEE International High Level Design Validation and Test Workshop (HLDVT'99).
18. J. Notbauer, Th. Albrecht, G. Niedrist, and S. Rohringer, "Verification and Management of a Multimillion-Gate Embedded Core Design", In the 36th Design Automation Conference, June 1999.
19. A. Österling, Th. Benner, R. Ernst, D. Herrmann, Th. Scholz, and W. Ye, "Hardware/Software Co-Design: Principles and Practice", Chapter: 'The COSYMA System". Kluwer Academic Publishers, 1997.
20. D. A. Patterson and, J. L. Hennessy, "Computer Organization and Design: The Hardware/Software Interface", Second Edition, Morgan Kaufmann Publishers, 1997.
21. L. Semeria and A. Ghosh, "Methodology for Hardware/Software Co-verification in C/C++", In the Asia South Pacific Design Automation Conference, January 2000.
22. K. Van Rompaey, D. Verkest, I. Bolsens and H. De Man, "CoWare - A Design Environment for Heterogeneous Hardware/Software Systems", In EURO-DAC'96, September 16-20, 1996.
23. S. Vercauteren, B. Lin and H. De Man, "Constructing Application-Specific Heterogeneous Embedded Architectures from Custom HW/SW Applications", In the 33rd Design Automation Conference, June 1996.
24. T. Y. Yen and W. Wolf, "Communication synthesis for distributed embedded systems", In International Conference on Computer Aided Design. IEEE Computer Society Press, 1995.
25. S. Yoo, J. Lee, J. Jung K. Rha, Y. Cho, and K. Choi, "Fast Prototyping of an IS-95 CDMA Cellular Phone: a Case Study", In the 6th Conference of Asia Pacific Chip Design Language, pp. 61-66, October 1999.
26. Arexsys, "Exploring details of system-level design", http://www.arexsvs.com
27. ARM, Inc. "AMBA Specification Overview", http://www.arm.com/ Pro+Peripherals/AMBA
28. Cadence, Inc. " Cadence Claims Front-End for System-On-A-Chip with Hardware and Software Co-Development Strategy", 1998, http://www.cadence. com/company/pr/archive98/l 1 02 98.ht ml
29. CARDtools Systems, "CARDtools in the Design Flow", http://www.cardtoolsxom/PUBLICATION/publicationindex. html
30. IBM, Inc. "28.4G Packet Routing Switch", Networking Technology Datasheets, http://www.chips.ibm.com/techlib/products/commun/datashee ts.html
31. IBM, Inc. "The CoreConnectTM Bus Architecture", 1999, http://www.chips.ibm.com:80/news/1999/990923/pdf/corecon 128-wp.pdf
32. Sun Microsystems, Inc. "MAJCTM Architecture Tutorial", white paper, 1999. http://www.sun. com/microeIectronics/MAJC
33. Synopsys, Inc., "Synopsys VHDL System Simulator", http://www.synopsys.com/products/simulation/vss-cs.html
34. ™ Architecture Document", 1997, http://www.vsia.com