-
1
-
-
0346655735
-
Deep submicrometer super self-aligned Si bipolar technology with 25.4 ps ECL
-
Jan
-
S. Konaka, M. Ugajin, and T. Matsuda, "Deep submicrometer super self-aligned Si bipolar technology with 25.4 ps ECL," IEEE Trans. Electron Devices, vol. 43, pp. 44-49, Jan. 1994.
-
(1994)
IEEE Trans. Electron Devices
, vol.43
, pp. 44-49
-
-
Konaka, S.1
Ugajin, M.2
Matsuda, T.3
-
2
-
-
0006664593
-
Advanced process device technology for 0.3-_mhigh-performance bipolar LSI's
-
June
-
Y. Tamaki, T. Shiba, T. Kure, K. Ohyu, and T. Nakamura, "Advanced process device technology for 0.3-_mhigh-performance bipolar LSI's," IEEE Trans. Electron Devices, vol. 39, pp. 1387-1391, June 1992.
-
(1992)
IEEE Trans. Electron Devices
, vol.39
, pp. 1387-1391
-
-
Tamaki, Y.1
Shiba, T.2
Kure, T.3
Ohyu, K.4
Nakamura, T.5
-
3
-
-
0030241287
-
A very small bipolar transistor technology with sidewall polycide base electrode for ECL-CMOS LSI's
-
Sept
-
T. Shiba, Y. Tamaki, T. Onai, Y. Kiyota, T. Kure, K. Ohyu, and T. Nakamura, "A very small bipolar transistor technology with sidewall polycide base electrode for ECL-CMOS LSI's," IEEE Trans. Electron Devices, vol. 43, pp. 1357-1363, Sept. 1996.
-
(1996)
IEEE Trans. Electron Devices
, vol.43
, pp. 1357-1363
-
-
Shiba, T.1
Tamaki, Y.2
Onai, T.3
Kiyota, Y.4
Kure, T.5
Ohyu, K.6
Nakamura, T.7
-
4
-
-
0035505631
-
Horizontal current bipolar transistor (HCBT): A new concept of silicon bipolar transistor technology
-
Nov
-
P. Biljanovic and T. Suligoj, "Horizontal current bipolar transistor (HCBT): a new concept of silicon bipolar transistor technology," IEEE Trans. Electron Devices, Vol.48, pp.2551-2554, Nov. 2001.
-
(2001)
IEEE Trans. Electron Devices
, vol.48
, pp. 2551-2554
-
-
Biljanovic, P.1
Suligoj, T.2
-
5
-
-
0042026500
-
Fabrication of horizontal current bipolar transistor (HCBT)
-
July
-
T. Suligoj, M. Koricic, P. Biljanovic, and K. L. Wang, "Fabrication of horizontal current bipolar transistor (HCBT)," IEEE Trans. Electron Devices, Vol.50, pp. 1645-1651, July 2003.
-
(2003)
IEEE Trans. Electron Devices
, vol.50
, pp. 1645-1651
-
-
Suligoj, T.1
Koricic, M.2
Biljanovic, P.3
Wang, K.L.4
-
6
-
-
15544362319
-
A novel low cost horizontal current bipolar transistor (HCBT) with the reduced parasitics
-
13-14 Sept
-
T. Suligoj, P. Biljanovic, J. K. O. Sin and K. L. Wang, "A novel low cost horizontal current bipolar transistor (HCBT) with the reduced parasitics," Proc. Bipolar/BiCMOS Circuits and Technology Meeting , 13-14 Sept. 2004, pp.36-39.
-
(2004)
Proc. Bipolar/BiCMOS Circuits and Technology Meeting
, pp. 36-39
-
-
Suligoj, T.1
Biljanovic, P.2
Sin, J.K.O.3
Wang, K.L.4
-
7
-
-
15544386458
-
A new HCBT with a partially etched collector
-
March
-
T. Suligoj, P. Biljanovic, J. K. O. Sin and K. L. Wang, "A new HCBT with a partially etched collector," IEEE Electron Device Lett., Vol.26, pp.200-202, March 2005.
-
(2005)
IEEE Electron Device Lett
, vol.26
, pp. 200-202
-
-
Suligoj, T.1
Biljanovic, P.2
Sin, J.K.O.3
Wang, K.L.4
-
8
-
-
23944443585
-
Horizontal Current Bipolar Transistor (HCBT) Process Variations for Future RF BiCMOS Applications
-
July
-
T. Suligoj, J. K. O. Sin and K. L. Wang, "Horizontal Current Bipolar Transistor (HCBT) Process Variations for Future RF BiCMOS Applications," IEEE Trans. Electron Devices, Vol.52, pp.1392-1398, July 2005.
-
(2005)
IEEE Trans. Electron Devices
, vol.52
, pp. 1392-1398
-
-
Suligoj, T.1
Sin, J.K.O.2
Wang, K.L.3
-
9
-
-
11144248829
-
Surface Accumulation Layer Bipolar Transistor (SALTran): A New Bipolar Transistor for Enhanced Current Gain and Reduced Hot Carrier Degradation
-
Sept
-
M. J. Kumar and V. Parihar, "Surface Accumulation Layer Bipolar Transistor (SALTran): A New Bipolar Transistor for Enhanced Current Gain and Reduced Hot Carrier Degradation," IEEE Trans. Device and Materials Reliability, Vol.4, pp.509-519, Sept. 2004.
-
(2004)
IEEE Trans. Device and Materials Reliability
, vol.4
, pp. 509-519
-
-
Kumar, M.J.1
Parihar, V.2
-
10
-
-
21644448434
-
Enhanced Current Gain in SiC Power BJTs using a novel Surface Accumulation Layer Transistor (SALTran) Concept
-
July
-
M. J. Kumar and V. Parihar, "Enhanced Current Gain in SiC Power BJTs using a novel Surface Accumulation Layer Transistor (SALTran) Concept," Microelectronic Engineering, Vol.81, pp.90-95, July 2005.
-
(2005)
Microelectronic Engineering
, vol.81
, pp. 90-95
-
-
Kumar, M.J.1
Parihar, V.2
-
11
-
-
20444501398
-
Realizing high current gain PNP transistors using a novel Surface Accumulation Layer Transistor (SALTran) concept
-
March
-
M. J. Kumar and V. Parihar, "Realizing high current gain PNP transistors using a novel Surface Accumulation Layer Transistor (SALTran) concept," IEE Proc. Circuits, Devices and Systems, Vol.152, pp. 178-182, March 2005.
-
(2005)
IEE Proc. Circuits, Devices and Systems
, vol.152
, pp. 178-182
-
-
Kumar, M.J.1
Parihar, V.2
-
12
-
-
27944433853
-
Enhanced Current Gain in SiC Power BJTs Using Surface Accumulation Layer Transistor (SALTran) Concept
-
D, Nov. 21-24
-
M. J. Kumar and V. Parihar, "Enhanced Current Gain in SiC Power BJTs Using Surface Accumulation Layer Transistor (SALTran) Concept," TENCON 2004, IEEE Region 10 Conference, Volume D, Nov. 21-24, 2004, pp. 199-200.
-
(2004)
TENCON 2004, IEEE Region 10 Conference
, pp. 199-200
-
-
Kumar, M.J.1
Parihar, V.2
-
14
-
-
2342471927
-
-
M. J. Kumar and V. Parihar, A New Surface Accumulation Layer Transistor(SALTran) Concept for Current Gain Enhancement in Bipolar Transistors, Proc. 17th International Conference on VLSI Design, 5-9 January 2004, pp.827-831.
-
M. J. Kumar and V. Parihar, A New Surface Accumulation Layer Transistor(SALTran) Concept for Current Gain Enhancement in Bipolar Transistors," Proc. 17th International Conference on VLSI Design, 5-9 January 2004, pp.827-831.
-
-
-
-
15
-
-
84945246727
-
A Novel High Current Gain Lateral PNP Transistor on SOI for Complimentary Bipolar Technology
-
ISDRS, Washington DC, USA, December 10-12
-
M. J. Kumar and V. Parihar, "A Novel High Current Gain Lateral PNP Transistor on SOI for Complimentary Bipolar Technology," 2003 International Semiconductor Device Research Symposium (ISDRS), Washington DC, USA, December 10-12, 2003, pp.268-269.
-
(2003)
2003 International Semiconductor Device Research Symposium
, pp. 268-269
-
-
Kumar, M.J.1
Parihar, V.2
-
16
-
-
33847133160
-
-
SUPREM4, Technology Modeling Associates, CA, USA, 2000.
-
SUPREM4, Technology Modeling Associates, CA, USA, 2000.
-
-
-
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