A new surface accumulation layer transistor(SALTran) concept for current gain enhancement in bipolar transistors

Proceedings of the IEEE International Conference on VLSI Design

Volumn 17, Issue , 2004, Pages 827-831

  Kumar, M Jagadesh ^a   Parihar, Vinod ^a  

^a INDIAN INSTITUTE OF TECHNOLOGY DELHI   (India)

Author keywords

[No Author keywords available]

Indexed keywords

CURRENT GAIN; CUT-OFF FREQUENCY; NOISE CURRENTS; WORK FUNCTIONS;

CHEMICAL VAPOR DEPOSITION; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; ETCHING; MOSFET DEVICES; PROCESS CONTROL; SEMICONDUCTOR JUNCTIONS;

BIPOLAR TRANSISTORS;

EID: 2342471927     PISSN: 10639667     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)

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3. K.Z. Chang, and C.Y. Wu, "A novel PHL-emitter bipolar transistor - fabrication and characterization," Solid-state Electronics, Vol.36, pp.1393-1399, October 1993.
4. B. Edholm, J. Olsson and A. Soderbarg, "A self-aligned lateral bipolar transistor realized on SIMOX material," IEEE Trans. on Electron Devices, vol.40, pp.2359-2360, Dec 1993.
5. R.S.Muller and T.I.Kamins, Device Electronics for Integrated Circuits, John Wiley & Sons, 2003.
6. ATHENA User's Manual, Silvaco Int., 2000.
7. ATLAS User's Manual, Silvaco Int., 2000