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Volumn 152, Issue 2, 2005, Pages 178-182
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Realising high-current gain p-n-p transistors using a novel surface accumulation layer transistor (SALTran) concept
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Author keywords
[No Author keywords available]
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Indexed keywords
CMOS INTEGRATED CIRCUITS;
COMPUTER SIMULATION;
LIGHT AMPLIFIERS;
OPTIMIZATION;
SEMICONDUCTOR MATERIALS;
VLSI CIRCUITS;
BIPOLAR TECHNOLOGIES;
ELECTRON CONCENTRATION;
PUSH-PULL CIRCUITS;
SURFACE ACCUMULATION LAYER TRANSISTOR (SALTRAN);
BIPOLAR TRANSISTORS;
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EID: 20444501398
PISSN: 13502409
EISSN: None
Source Type: Conference Proceeding
DOI: 10.1049/ip-cds:20045015 Document Type: Conference Paper |
Times cited : (3)
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References (11)
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