Survey of noise performances and scaling effects in deep submicrometer CMOS devices from different foundries

IEEE Transactions on Nuclear Science

Volumn 52, Issue 6, 2005, Pages 2733-2740

  Re, Valerio ^b,c   Manghisoni, Massimo ^b,c   Ratti, Lodovico ^a,c,d   Speziali, Valeria ^a,c,d   Traversi, Gianluca ^b,c  

^a IEEE

^b UNIVERSITY OF BERGAMO   (Italy)

^c INFN SEZIONE DI PAVIA   (Italy)

^d UNIVERSITY OF PAVIA   (Italy)

Author keywords

CMOS; Deep submicron; Front end electronics; MOSFET; Noise

Indexed keywords

CAPACITANCE; FOUNDRIES; THERMAL NOISE;

DEEP SUBMICRON; FRONT-END ELECTRONICS; SCALING EFFECTS;

CMOS INTEGRATED CIRCUITS;

EID: 33144481325     PISSN: 00189499     EISSN: None     Source Type: Journal    
DOI: 10.1109/TNS.2005.862771     Document Type: Conference Paper

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