Fast comparisons of circuit implementations

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 13, Issue 12, 2005, Pages 1329-1339

  Karandikar, Shrirang K ^b   Sapatnekar, Sachin S ^a,c  

^a IEEE

^b IBM AUSTIN RESEARCH LABORATORY   (United States)

^c University of Minnesota   (United States)

Author keywords

Circuit optimization; Cost delay tradeoffs; Delay estimation; Dynamic programming; Gate sizing; Logical effort; Performance estimation; Transistor sizing

Indexed keywords

CIRCUIT OPTIMIZATION; COST-DELAY TRADEOFFS; DELAY ESTIMATION; GATE SIZING; LOGICAL EFFORT; PERFORMANCE ESTIMATION; TRANSISTOR SIZING;

COSTS; DIGITAL CIRCUITS; DYNAMIC PROGRAMMING; ESTIMATION; METRIC SYSTEM; OPTIMIZATION;

INTEGRATED CIRCUITS;

EID: 31644436243     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2005.862727     Document Type: Article

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