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Volumn , Issue , 2002, Pages 677-682

Improving placement under the constant delay model

Author keywords

[No Author keywords available]

Indexed keywords

AREA SAVINGS; CONSTANT DELAYS; EDGE WEIGHTS; PLACEMENT PROBLEMS; PLACEMENT PROCESS; RECURSIVE PARTITIONING; TIMING CLOSURES; WEIGHTED SUM;

EID: 3042583305     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2002.998372     Document Type: Conference Paper
Times cited : (4)

References (10)
  • 2
    • 0022231945 scopus 로고
    • TILOS: A polynomial programming approach to transistor sizing
    • Fishburn, J. and Dunlop, A.: "TILOS: A polynomial programming approach to transistor sizing", Proc. ICCAD-85, 1985
    • (1985) Proc. ICCAD-85
    • Fishburn, J.1    Dunlop, A.2
  • 3
    • 0021784846 scopus 로고
    • A procedure for placement of standard cell vlsi circuits
    • Dunlop, A.; Kernighan, B.: "A Procedure for Placement of Standard Cell VLSI Circuits", IEEE Transactions on CAD, vol. 4, no. 1, 1985
    • (1985) IEEE Transactions on CAD , vol.4 , Issue.1
    • Dunlop, A.1    Kernighan, B.2
  • 4
    • 0026989865 scopus 로고
    • A nearly optimal algorithm for technology mapping minimizing area under delay constraints
    • K. Chaudhary, and M. Pedram: "A nearly optimal algorithm for Technology Mapping minimizing Area under Delay Constraints", Proc. 29th Design Automation Conference, 1992
    • (1992) Proc. 29th Design Automation Conference
    • Chaudhary, K.1    Pedram, M.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.