Fast comparisons of circuit implementations

Proceedings - Design, Automation and Test in Europe Conference and Exhibition

Volumn 2, Issue , 2004, Pages 910-915

  Karandikar, Shrirang K ^a   Sapatnekar, Sachin S ^a  

^a UNIVERSITY OF MINNESOTA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CIRCUIT DELAY; COMBINATIONAL BENCHMARKING; DIGITAL DESIGNS; AVERAGE ERRORS; CIRCUIT IMPLEMENTATION; CIRCUIT PERFORMANCE; CRITICAL PATHS; POST PROCESSING; TIMING SPECIFICATIONS; TRANSISTOR SIZING;

ALGORITHMS; BENCHMARKING; BOUNDARY VALUE PROBLEMS; COMPUTATIONAL METHODS; DIGITAL CIRCUITS; GAIN CONTROL; GATES (TRANSISTOR); LINEAR PROGRAMMING; MAPPING; OPTIMIZATION; ROUTERS; ELECTRIC NETWORK ANALYSIS; EXHIBITIONS; TOOLS;

CIRCUIT THEORY; DESIGN;

EID: 3042517220     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2004.1269005     Document Type: Conference Paper

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