Fast estimation of area-delay trade-offs in circuit sizing

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2005, Pages 3575-3578

  Karandikar, Shrirang K ^a   Sapatnekar, Sachin S ^b  

^a IBM AUSTIN RESEARCH LABORATORY   (United States)

^b University of Minnesota   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

AVERAGE ERRORS; CIRCUIT SIZING; FAST ESTIMATION; TRADE-OFF CURVES;

EID: 31644448859     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2005.1465402     Document Type: Conference Paper

References (10)

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