Gain-based technology mapping for discrete-size cell libraries

Proceedings - Design Automation Conference

Volumn , Issue , 2003, Pages 574-579

  Hu, Bo ^a   Watanabe, Yosinori ^b   Kondratyev, Alex ^b   Marek Sadowska, Malgorzata ^a  

^a University of California   (United States)

^b CADENCE DESIGN SYSTEMS   (United States)

Author keywords

Gain; Logic effort; Technology mapping

Indexed keywords

ALGORITHMS; COMPUTER AIDED DESIGN; COMPUTER AIDED ENGINEERING; HEURISTIC METHODS;

TECHNOLOGY MAPPING;

APPLICATION SPECIFIC INTEGRATED CIRCUITS;

EID: 0043136596     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/775978.775979     Document Type: Conference Paper

References (16)

1. F. Beeftink, P. Kudva, D. Kung, and L. Stok, "Gate-Size Selection for Standard Cell Libraries", in Proc ICCAD, 1998, pp. 545-550.
2. K. D. Boese, A. B. Kahng, and S. Mantik, "On the relevance of Wire Load Models", Proc. SLIP 2001, pp. 91-98.
3. K. Chaudhary, M. Pedram, "A Near-Optimal Algorithm for Technology Mapping Minimizing Area under Delay Constraints", in Proc. DAC, 1992, pp. 492-498.
4. J. Grodstein, E. Lehman, H. Harkness, B. Grundmann, Y. Watanabe, "A Delay Model for Logic Synthesis of Continuously-Sized Networks", in Proc. ICCAD, pp. 458-462, 1995.
5. C. M. Hoffman and M. J. O'Donnell, "Pattern Matching in Trees", Journal of the Association for Computing Machinary, pages 68-95, January 1982.
6. D. J. Jongeneel, R. Often, Y. Watanabe, and R. K. Brayton, "Area and Search Space Control for Technology Mapping", DAC 2000.
7. K. Keutzer, "DAGON: Technology Binding and Local Optimization by DAG Matching". Proc DAC, 1987, pp.341-347.
8. Y. Kukimoto, R. K. Brayton, P. Sawkar, "Delay-optimal technology mapping by dag covering", Proc. DAC, June 1998.
9. E. Lehman, Y. Watanabe, J. Grodstein, and H. Harkness, "Logic Decomposition during Technology Mapping", IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, pages 813-833, 1997.
10. A. Lu, G. Stenz, H. Eisenmann, F. M. Johannes, "Technology mapping for simultaneous gate and interconnect Optimization", IEE Proc. -Comput. Digit. Tech. Vol. 146, No. 1. 1, Jan. 1999.
11. P. Rezvani, A. H. Ajami, M. Pedram, and H. Savoj, "LEOPARD: A Logical Effort-based fanout OPtimizer for Area and Delay", in Proc. ICCAD, 1999, pp. 516-518.
12. R. Rudell, "Logic Synthesis for VLSI Design", Memo UCB/ ERL M89/49, U. C. Berkeley, 1989.
13. I. Sutherland, R. Sproull, "The theory of logical effort: designing for speed on the back of an envelope", Advanced Research in VLSI, 1991.
14. L. Stok, M. A. Iyer, and A.J. Sullivan, "Wavefront technology mapping", Proc. DATE, pp. 531-536, 1999.
15. E. Sentovich, K. Singh, C. Moon, H. Savoj, R. Brayton, and A. Sangiovanni-Vincentelli, "Sequential circuit design using synthesis and optimization", in IEEE Int. Conf. Comput. Design, 1992.
16. H. J. Touati, "Performance Oriented Technology Mapping", Ph. D thesis, UC Berkeley, 1990, pp. 79-97.