Multilevel Flash cells and their Trade-offs

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 1996, Pages 169-172

  Eitan, Boaz ^a   Kazerounian, Reza ^a   Roy, Anirban ^a   Crisenza, Giuseppe ^b   Cappelletti, Paolo ^b   Modelli, Alberto ^b  

^a WSI   (United States)

^b STMICROELECTRONICS   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

ECONOMIC AND SOCIAL EFFECTS; MEMORY ARCHITECTURE; COMPUTER PROGRAMMING; ELECTRON TUNNELING; HOT CARRIERS; LOGIC GATES;

CELL-BE; CELL/B.E; CELL/BE; COMMON GROUND; FLASH CELL; MULTILEVEL PROGRAMMING; MULTILEVELS; PROGRAMMING MECHANISM; SPLIT GATES; TRADE OFF;

NAND CIRCUITS; NONVOLATILE STORAGE;

CHANNEL HOT ELECTRON INJECTION; MULTILEVEL FLASH CELLS;

EID: 0030387349     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEDM.1996.553147     Document Type: Conference Paper

References (25)

1. B. Venkatesh et al., "A 55ns 0.35jim 5V-only 16M Hash Memory with Deep-Power-Down" ISSCC 96 TP 2.7 p. 44.
2. S. Kobayashi et al., "A 3.3V-Only 16 Mb DINOR Flash Memory," ISSCC 95, TA 7.2, p. 122.
3. H. Miwa et al., "A 140mm2 64Mb AND Flash Memory with A 0.4nm Technology," ISSCC 96, TP 2.2, p. 34.
4. K. S. Kim et al., "A Novel Dual String NOR (DuSNOR) Memory Cell Technology Scalable to the 256 Mbit and 1 Gbit Flash Memories," IEDM 95, Paper 11.1, p. 263.
5. A. Roy et al.. Patent Pending.
6. R. Cernea et al., "A 34Mb 3.3V Serial Hash EEPROM for Solid-State Disk Applications," ISSCC 95. TA 7.4, p. 126.
7. T. S. Jung et al., "A 3.3V 128Mb Multi-Level NAND Hash Memory for Mass Storage Applications," ISSCC 96, TA 2.1, p. 32.
8. M. Bauer et al., "A Multilevel-Cell 32Mb Hash Memory". ISSCC 95, p. 132.
9. B. Eitan, "Cell Concepts and Array Architectures" Hash Memory Tutorial, NVSM 95.
10. J. D. Bude et al., "EEPROM/Hash Sub 3.0V Drain-Source Bias Hot Carrier Writing". IEDM 95 3.7, p. 989.
11. [ I I ] A. Nozoe et al., "A 3.3V High-Density AND Hash Memory with lms/512B Erase & Program Time", ISSCC 95. TA 7.3. p. 124.
12. H. Kume et al.. "A Hash Erase EEPROM Cell With An Asymmetric." IEDM 87. Paper 25.8, p. 560.
13. R. Kazerounian et al., "A 5 Volt High Density Poly-Poly Erase Hash EPROM Cell", IEDM 88, p. 436.
14. 2 3.3V 64Mb Hash Memory with FN-NOR type 4-level Cell". ISSCC 96. TP 2.3, p. 36.
15. P. Cappelletti et al., "Failure Mechanisms of Hash Cell in Program/Erase Cycling", IEDM 94, Paper 11.1, p. 291.
16. H. Onoda et al.. "A Novel Cell Structure Suitable For A 3V Operation, Sector Erase Flash Memory," IEDM 92, Paper 24 3 p 599.
17. K Yoshikawa. "Impact of Cell Threshold Voltage Distribution in the Array of Hash Memories on Scaled and Multilevel Hash Cell Design," V L S I Technology Symp. 96, Paper 24.3, p. 240.
18. 2 Self-Aligned Contactless Memory Cell Technology Suitable for 256-Mbit Hash Memories," IEDM 94, Paper 3.8, p. 921.
19. H. Shirai et al., "A 0.54|Am2 Self-Aligned, HSG Hoating Gate Cell (SAHF Cell) for 256Mbit Flash Memories," IEDM 95, Paper 27.1. p. 653.
20. B. Eitan et al., "Alternate Metal Virtual Ground (AMG)-A New Scaling Concept for Very High-Density EPROM's," I E E E E D L Vol. 12, No. 8, p 450,1991.
21. D. J. Lee et al., "An 18Mb Serial Hash EEPROM for Solid-State Disk Applications," VLSI Circuits Symp. 94, Paper 6.1, p. 59.
22. K Takeuchi et al., "A Double-Level-Vth Select Gate Array Architecture for Multilevel NAND Hash Memories," IEEE JSSC Vol. 31, No. 4. p. 6021996.
23. K Kohds et. al. Patent 5,021,999.
24. Y. Ma et al, "A Dual-bit Split-Gate EEPROM (DSG) Cell in Contactless Array for Single Vcc High Density Hash Memories", IEDM 95,3.5, p. 57.
25. R. Kazerounian Patent Pending.