Designing self test programs for embedded DSP cores

Proceedings - Design, Automation and Test in Europe Conference and Exhibition

Volumn 2, Issue , 2004, Pages 816-821

  Rizk, Hani ^a   Papachristou, Chris ^a   Wolff, Francis ^a  

^a Case Western Reserve University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

AUTOMATED TEST EQUIPMENTS (ATE); EMBEDDED CORES; PSEUDORANDOM PATTERNS; SYSTEM-ON-CHIP (SOC) TECHNOLOGY; DSP CORE; EMBEDDED DSP; PROGRAM TEMPLATES; PSEUDO RANDOM; SELF TEST; TEST METRICS; TEST PROGRAM;

AUTOMATIC TESTING; COMPUTER PROGRAMMING; COMPUTER SIMULATION; DATABASE SYSTEMS; ELECTRIC FAULT CURRENTS; INFORMATION THEORY; ITERATIVE METHODS; RANDOM PROCESSES; DESIGN; EXHIBITIONS; TEST FACILITIES;

ELECTRICAL ENGINEERING; ITERATIVE METHODS;

EID: 3042569000     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2004.1268982     Document Type: Conference Paper

References (11)

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