Reducing average and peak test power through scan chain modification

Journal of Electronic Testing: Theory and Applications (JETTA)

Volumn 19, Issue 4, 2003, Pages 457-467

  Sinanoglu, Ozgur ^a   Bayraktaroglu, Ismet ^a   Orailoglu, Alex ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

Average test power; Peak test power; Scan chain modification; Scan testing; Test power reduction

Indexed keywords

FLIP FLOP CIRCUITS; LOGIC GATES; SWITCHING CIRCUITS; VECTORS;

SCAN CHAIN MODIFICATION; SCAN TESTING; SYSTEM ON A CHIP;

INTEGRATED CIRCUIT TESTING;

EID: 0041473850     PISSN: 09238174     EISSN: None     Source Type: Journal    
DOI: 10.1023/A:1024600311740     Document Type: Article

References (11)

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