-
1
-
-
0042721073
-
Minimized power consumption for scan based BIST
-
H.J. Wunderlich and S. Gerstendorfer, "Minimized power consumption for scan based BIST", in ITC, pp. 85-94, 1999.
-
(1999)
ITC
, pp. 85-94
-
-
Wunderlich, H.J.1
Gerstendorfer, S.2
-
2
-
-
84948953596
-
Inserting test points to control peak power during scan testing
-
R. Sankaralingam and N.A. Touba, "Inserting Test Points to Control Peak Power During Scan Testing", in DFT, pp. 138-146, 2002.
-
(2002)
DFT
, pp. 138-146
-
-
Sankaralingam, R.1
Touba, N.A.2
-
3
-
-
0033347952
-
An input control technique for power reduction in scan circuits during test application
-
T. Huang and K. Lee, "An input control technique for power reduction in scan circuits during test application", in ATS, pp. 315-320, 1999.
-
(1999)
ATS
, pp. 315-320
-
-
Huang, T.1
Lee, K.2
-
4
-
-
0011840118
-
Minimisation of power dissipation during test application in full-scan sequential circuits using primary input freezing
-
N. Nicolici, B. M. Al-Hashimi and A. C. Williams, "Minimisation of power dissipation during test application in full-scan sequential circuits using primary input freezing", IEEE TCOMP, vol. 47, n. 2. pp. 256-262, 1998.
-
(1998)
IEEE TCOMP
, vol.47
, Issue.2
, pp. 256-262
-
-
Nicolici, N.1
Al-Hashimi, B.M.2
Williams, A.C.3
-
5
-
-
0034479271
-
Adapting scan architectures for low power operation
-
L. Whetsel, "Adapting scan architectures for low power operation", in ITC, pp. 863-872, 2000.
-
(2000)
ITC
, pp. 863-872
-
-
Whetsel, L.1
-
6
-
-
0035018934
-
A modified clock scheme for a low power BIST test pattern generator
-
Y. Bonhomme, P. Girard, L. Guiller, C. Landrault, S. Pravossoudovitch and H.J. Wunderlich, "A modified clock scheme for a low power BIST test pattern generator", in VTS, pp. 306-311, 2001.
-
(2001)
VTS
, pp. 306-311
-
-
Bonhomme, Y.1
Girard, P.2
Guiller, L.3
Landrault, C.4
Pravossoudovitch, S.5
Wunderlich, H.J.6
-
7
-
-
0001321331
-
Techniques for minimizing power dissipation in scan and combinational circuits during test application
-
V. Dabholkar, S. Chakravarty, I. Pomeranz and S. M. Reddy, "Techniques for minimizing power dissipation in scan and combinational circuits during test application", IEEE TCAD, vol. 17, n. 12, pp. 1325-1333, 1998.
-
(1998)
IEEE TCAD
, vol.17
, Issue.12
, pp. 1325-1333
-
-
Dabholkar, V.1
Chakravarty, S.2
Pomeranz, I.3
Reddy, S.M.4
-
8
-
-
0033751823
-
Adapting scan architectures for low power operation
-
R. Sankaralingam, R. R. Oruganti and N. A. Touba, "Adapting scan architectures for low power operation", in VTS, pp. 35-40, 2000.
-
(2000)
VTS
, pp. 35-40
-
-
Sankaralingam, R.1
Oruganti, R.R.2
Touba, N.A.3
-
9
-
-
0034995123
-
Reducing power dissipation during test using scan chain disable
-
R. Sankaralingam, B. Pouya and N. A. Touba, "Reducing Power Dissipation During Test Using Scan Chain Disable", in VTS, pp. 319-324, 2001.
-
(2001)
VTS
, pp. 319-324
-
-
Sankaralingam, R.1
Pouya, B.2
Touba, N.A.3
-
10
-
-
84948443429
-
Test power reduction through minimization of scan chain transitions
-
O. Sinanoglu, I. Bayraktaroglu and A. Orailoglu, "Test Power Reduction Through Minimization of Scan Chain Transitions", in VTS, pp. 166-171, 2002.
-
(2002)
VTS
, pp. 166-171
-
-
Sinanoglu, O.1
Bayraktaroglu, I.2
Orailoglu, A.3
-
11
-
-
0036443091
-
Scan power reduction through test data transition frequency analysis
-
O. Sinanoglu, I. Bayraktaroglu and A. Orailoglu, "Scan Power Reduction Through Test Data Transition Frequency Analysis," in ITC, pp. 844-850, 2002.
-
(2002)
ITC
, pp. 844-850
-
-
Sinanoglu, O.1
Bayraktaroglu, I.2
Orailoglu, A.3
-
12
-
-
0041473850
-
Reducing average and peak test power through scan chain modification
-
O. Sinanoglu, I. Bayraktaroglu and A. Orailoglu, "Reducing Average and Peak Test Power Through Scan Chain Modification", JETTA, 2003.
-
(2003)
JETTA
-
-
Sinanoglu, O.1
Bayraktaroglu, I.2
Orailoglu, A.3
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