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Volumn , Issue , 1999, Pages 315-320

Input control technique for power reduction in scan circuits during test application

Author keywords

[No Author keywords available]

Indexed keywords

INPUT CONTROL TECHNIQUES; SCAN CIRCUITS;

EID: 0033347952     PISSN: 10817735     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Article
Times cited : (34)

References (15)
  • 1
    • 0000117401 scopus 로고
    • ATPG for heat dissipation minimization during test application
    • S. Wang and S. K. Gupta "ATPG for Heat Dissipation Minimization During Test Application", Int'l Test Conf., pp.250-258 1994
    • (1994) Int'l Test Conf. , pp. 250-258
    • Wang, S.1    Gupta, S.K.2
  • 2
    • 0031376352 scopus 로고    scopus 로고
    • DS- LFSR a new BISTTPG for low heat dissipation
    • S. Wang and S. K. Gupta "DS- LFSR A New BISTTPG for Low heat Dissipation", Int'l Test Conf., pp.848-857 1997
    • (1997) Int'l Test Conf. , pp. 848-857
    • Wang, S.1    Gupta, S.K.2
  • 3
    • 0032317778 scopus 로고    scopus 로고
    • A test pattern generation methodology for low power consumption
    • F. Corno, P. Prinetto, M. Rebaudengo and M. S. Reorda "A Test Pattern Generation Methodology for Low Power Consumption", VLSI Test Symp., pp.453-457 1998
    • (1998) VLSI Test Symp. , pp. 453-457
    • Corno, F.1    Prinetto, P.2    Rebaudengo, M.3    Reorda, M.S.4
  • 4
    • 0027544156 scopus 로고
    • Transition density: A new measure of activity in digital circuits
    • F. Najm "Transition Density: A New Measure of Activity in Digital Circuits", IEEE Trans. on CAD, vol. 12, pp.310-323 1993
    • (1993) IEEE Trans. on CAD , vol.12 , pp. 310-323
    • Najm, F.1
  • 5
    • 0028728068 scopus 로고
    • Two techniques for minimizing power dissipationin scan circuits during test application
    • S. Chakravarty and V. P. Dabholkar "Two Techniques for Minimizing Power Dissipationin Scan Circuits During Test Application", IEEE Asian Test Symp., pp.324-329 1994
    • (1994) IEEE Asian Test Symp. , pp. 324-329
    • Chakravarty, S.1    Dabholkar, V.P.2
  • 6
    • 0001321331 scopus 로고    scopus 로고
    • Techniques for minimizing power dissipation in scan and combinational circuits during test application
    • V. Dabholkar, S. Chakravarty, I. Pomeranz and S. Reddy "Techniques for Minimizing Power Dissipation in Scan and Combinational Circuits During Test Application", IEEE Trans. on Computer-Aided Design, vol. 17, no. 12, pp.1325-1333 1998
    • (1998) IEEE Trans. on Computer-Aided Design , vol.17 , Issue.12 , pp. 1325-1333
    • Dabholkar, V.1    Chakravarty, S.2    Pomeranz, I.3    Reddy, S.4
  • 8
    • 0031561210 scopus 로고    scopus 로고
    • Reduction of power consumption during test application by test vector ordering
    • P. Girard, C. Landrault, S. Pravossoudovitch and D. Severac "Reduction of Power Consumption during Test Application by Test Vector Ordering", Electronics Letters, vol. 33, no. 21, pp.1752-1754 1997
    • (1997) Electronics Letters , vol.33 , Issue.21 , pp. 1752-1754
    • Girard, P.1    Landrault, C.2    Pravossoudovitch, S.3    Severac, D.4
  • 9
    • 0026130970 scopus 로고
    • A new transition count method for testing of logic circuits
    • K. I. Diamantaras and N. K. Jha "A New Transition Count Method for Testing of Logic Circuits", IEEE Trans. CAD, vol. 10, no. 3, pp.407-410 1991
    • (1991) IEEE Trans. CAD , vol.10 , Issue.3 , pp. 407-410
    • Diamantaras, K.I.1    Jha, N.K.2
  • 11
    • 0012175461 scopus 로고
    • A systematic method to classify scan cells
    • K.-J. Lee, M.-H. Lu and J.-F. Wang "A Systematic Method to Classify Scan Cells", Asian Test Symp., pp.219-224 1993
    • (1993) Asian Test Symp. , pp. 219-224
    • Lee, K.-J.1    Lu, M.-H.2    Wang, J.-F.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.