Design verification by test vectors and arithmetic transform universal test set

IEEE Transactions on Computers

Volumn 53, Issue 5, 2004, Pages 628-

  Radecka, Katarzyna ^a   Zilic, Zeljko ^b  

^a Dept of Electrical and Computer Engineering   (Canada)

^b MCGILL UNIVERSITY   (Canada)

Author keywords

Arithmetic transform; Error modeling; Reed Muller transform; Spectral methods; Universal test set; Verification; Walsh Hadamard transform

Indexed keywords

COMPUTER SIMULATION; CONSTRAINT THEORY; DECISION TABLES; DIGITAL ARITHMETIC; ERROR DETECTION; POLYNOMIALS;

ARITHMETIC TRANSFORM UNIVERSAL TEST SET; DECISION DIAGRAMS; DESIGN VERIFICATION; TEST VECTORS;

FAULT TOLERANT COMPUTER SYSTEMS;

EID: 3042527536     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/TC.2004.1275301     Document Type: Article

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