Using arithmetic transform for verification of datapath circuits via error modeling

Proceedings of the IEEE VLSI Test Symposium

Volumn , Issue , 2000, Pages 271-277

  Radecka, Katarzyna ^a   Zilic, Zeljko ^a  

^a MCGILL UNIVERSITY   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

DIGITAL ARITHMETIC; ERROR ANALYSIS; GRAPH THEORY; INTEGRAL EQUATIONS; MATHEMATICAL MODELS; MATHEMATICAL TRANSFORMATIONS; POLYNOMIALS; VECTORS;

ARITHMETIC CIRCUITS; ARITHMETIC TRANSFORM; DATAPATH CIRCUITS; ERROR MODEL; REED-MULLER POLYNOMIALS;

INTEGRATED CIRCUIT TESTING;

EID: 0033742118     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Article

References (9)