Identifying redundant wire replacements for synthesis and verification

Proceedings - 7th Asia and South Pacific Design Automation Conference, 15th International Conference on VLSI Design, ASP-DAC/VLSI Design 2002

Volumn , Issue , 2002, Pages 517-523

  Radecka, K ^a   Zilic, Z ^a  

^a MCGILL UNIVERSITY   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED DESIGN; EMBEDDED SYSTEMS; REDUNDANCY;

ARITHMETIC TRANSFORM; DON'T-CARES; ERROR-CORRECTING; FAULT COVERAGES; REDUNDANCY IDENTIFICATIONS; REDUNDANT FAULTS; SATISFIABILITY; TEST GENERATIONS;

DESIGN;

EID: 3042669484     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASPDAC.2002.994972     Document Type: Conference Paper

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