Identifying redundant gate replacements in verification by error modeling

IEEE International Test Conference (TC)

Volumn , Issue , 2001, Pages 803-812

  Radecka, Katarzyna ^a   Zilic, Zeljko ^a  

^a MCGILL UNIVERSITY   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

APPROXIMATION THEORY; ERROR ANALYSIS; LOGIC GATES; MATHEMATICAL MODELS; MATHEMATICAL TRANSFORMATIONS; REDUNDANCY; SEMICONDUCTOR DEVICE TESTING;

ERROR MODELING; WIRE REPLACEMENT FAULTS;

COMBINATORIAL CIRCUITS;

EID: 0035681198     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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