A minimal universal test set for self-test of EXOR-sum-of-products circuits

IEEE Transactions on Computers

Volumn 49, Issue 3, 2000, Pages 267-276

  Kalay, Ugur ^b   Hall, Douglas V ^a,b   Perkowski, Marek A ^a,b  

^a IEEE   (United States)

^b Department of Electrical and Computer Engineering   (United States)

Author keywords

AND EXOR realizations; Built in self test (BIST); Design for testing (DFT); Easily testable combinational networks; Reed Muller expressions; Self testable circuits; Single stuck at fault model; Test pattern generation; Universal test set

Indexed keywords

BUILT-IN SELF TEST; CONTROLLABILITY; DESIGN FOR TESTABILITY; ELECTRIC NETWORK ANALYSIS; INTEGRATED CIRCUIT TESTING; MATHEMATICAL MODELS; OBSERVABILITY;

SELF-TESTABLE CIRCUITS;

LOGIC CIRCUITS;

EID: 0033742567     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/12.841130     Document Type: Article

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