-
1
-
-
2342587244
-
Fault detection in redundant circuits
-
Feb.
-
A. D. Friedman, "Fault detection in redundant circuits," IEEE Trans. Electron. Comput., vol. EC-16, pp. 99-100, Feb. 1967.
-
(1967)
IEEE Trans. Electron. Comput.
, vol.EC-16
, pp. 99-100
-
-
Friedman, A.D.1
-
2
-
-
0012989062
-
DDQ yield loss inevitable?
-
Oct.
-
DDQ yield loss inevitable?," in Proc. Int. Test Conf., Oct. 1994, pp. 572-579.
-
(1994)
Proc. Int. Test Conf.
, pp. 572-579
-
-
Davidson, S.1
-
3
-
-
0024902656
-
Identification of undetectable faults in combinational circuits
-
Oct.
-
M. Harihara and P. R. Menon, "Identification of undetectable faults in combinational circuits," in Proc. Int. Conf. Comput. Design, Oct. 1989, pp. 290-293.
-
(1989)
Proc. Int. Conf. Comput. Design
, pp. 290-293
-
-
Harihara, M.1
Menon, P.R.2
-
4
-
-
84941363915
-
Redundancy removal and simplification of combinational circuits
-
Apr.
-
P. R. Menon and H. Ahuja, "Redundancy removal and simplification of combinational circuits," in Dig. Pap., IEEE VLSI Test Symp., Apr. 1992, pp. 268-273.
-
(1992)
Dig. Pap., IEEE VLSI Test Symp.
, pp. 268-273
-
-
Menon, P.R.1
Ahuja, H.2
-
5
-
-
0020923381
-
On the acceleration of test generation algorithms
-
Dec.
-
H. Fujiwara and T. Shimono, "On the acceleration of test generation algorithms," IEEE Trans. Comput., vol. C-32, pp. 1137-1114, Dec. 1983.
-
(1983)
IEEE Trans. Comput.
, vol.C-32
, pp. 1137-11114
-
-
Fujiwara, H.1
Shimono, T.2
-
6
-
-
0002551468
-
SMART and FAST: Test generation for VLSI scan-design circuits
-
Aug.
-
M. Abramovici, J. J. Kulikowski, P. R. Menon, and D. T. Miller, "SMART and FAST: Test generation for VLSI scan-design circuits," IEEE Design Test Comput., pp. 53-54, Aug. 1986.
-
(1986)
IEEE Design Test Comput.
, pp. 53-54
-
-
Abramovici, M.1
Kulikowski, J.J.2
Menon, P.R.3
Miller, D.T.4
-
8
-
-
0024703343
-
Improved deterministic test pattern generation with applications to redundancy identification
-
July
-
M. H. Schulz and E. Auth, "Improved deterministic test pattern generation with applications to redundancy identification," IEEE Trans. Computer-Aided Design, vol. 8, pp. 811-816, July 1989.
-
(1989)
IEEE Trans. Computer-Aided Design
, vol.8
, pp. 811-816
-
-
Schulz, M.H.1
Auth, E.2
-
9
-
-
0025481720
-
A method to calculate necessary assignments in algorithmic test pattern generation
-
Sept.
-
J. Rajski and H. Cox, "A method to calculate necessary assignments in algorithmic test pattern generation," in Proc. Int. Test Conf., Sept. 1990, pp. 25-34.
-
(1990)
Proc. Int. Test Conf.
, pp. 25-34
-
-
Rajski, J.1
Cox, H.2
-
10
-
-
0026677403
-
Search state equivalence for redundancy identification and test generation
-
Oct.
-
J. Giraldi and M. L. Bushnell, "Search state equivalence for redundancy identification and test generation," in Proc. Int. Test Conf., Oct. 1991, pp. 184-193.
-
(1991)
Proc. Int. Test Conf.
, pp. 184-193
-
-
Giraldi, J.1
Bushnell, M.L.2
-
11
-
-
84961249468
-
Recursive learning: An attractive alternative to the decision tree for test generation in digital circuits
-
Sept.
-
W. Kunz and D. K. Pradhan, "Recursive learning: An attractive alternative to the decision tree for test generation in digital circuits," in Proc. Int. Test Conf., Sept. 1992, pp. 816-825.
-
(1992)
Proc. Int. Test Conf.
, pp. 816-825
-
-
Kunz, W.1
Pradhan, D.K.2
-
12
-
-
0027634569
-
A transitive closure algorithm for test generation
-
July
-
S. T. Chakradhar, V. D. Agrawal, and S. G. Rothweiler, "A transitive closure algorithm for test generation," IEEE Trans. Computer-Aided Design, vol. 12, pp. 1015-1028, July 1993.
-
(1993)
IEEE Trans. Computer-Aided Design
, vol.12
, pp. 1015-1028
-
-
Chakradhar, S.T.1
Agrawal, V.D.2
Rothweiler, S.G.3
-
13
-
-
0346382368
-
One-pass redundancy identification and removal
-
Sept.
-
M. Abramovici and M. A. Iyer, "One-pass redundancy identification and removal," in Proc. Int. Test Conf., Sept. 1992, pp. 807-815.
-
(1992)
Proc. Int. Test Conf.
, pp. 807-815
-
-
Abramovici, M.1
Iyer, M.A.2
-
14
-
-
0028115179
-
Low-cost redundancy identification for combinational circuits
-
Jan.
-
M. A. Iyer and M. Abramovici, "Low-cost redundancy identification for combinational circuits," in Proc. 7th. Int. Conf. VLSI Design, Jan. 1994, pp. 315-318.
-
(1994)
Proc. 7th. Int. Conf. VLSI Design
, pp. 315-318
-
-
Iyer, M.A.1
Abramovici, M.2
-
15
-
-
2342662640
-
-
Ph.D. dissertation, ECE Depart., Illinois Inst. Technol., Chicago, IL, July
-
M. A. Iyer, "On redundancy and untestability in sequential circuits," Ph.D. dissertation, ECE Depart., Illinois Inst. Technol., Chicago, IL, July 1995.
-
(1995)
On Redundancy and Untestability in Sequential Circuits
-
-
Iyer, M.A.1
-
16
-
-
0016485480
-
Polynomially complete fault detection problems
-
Mar.
-
O. H. Ibarra and S. K. Sahni, "Polynomially complete fault detection problems," IEEE Trans. Comput., vol. C-24, pp. 242-249, Mar. 1975.
-
(1975)
IEEE Trans. Comput.
, vol.C-24
, pp. 242-249
-
-
Ibarra, O.H.1
Sahni, S.K.2
-
17
-
-
0026716904
-
The best flip-flops to scan
-
Oct.
-
M. Abramovici, J. J. Kulikowski, and R. K. Roy, "The best flip-flops to scan," in Proc. Int. Test Conf., Oct. 1991, pp. 166-173.
-
(1991)
Proc. Int. Test Conf.
, pp. 166-173
-
-
Abramovici, M.1
Kulikowski, J.J.2
Roy, R.K.3
-
18
-
-
0026839264
-
Dynamic redundancy Identification in automatic test generation
-
Mar.
-
M. Abramovici, D. T. Miller, and R. K. Roy, "Dynamic redundancy Identification in automatic test generation," IEEE Trans. Computer-Aided Design, pp. 404-407, Mar. 1992.
-
(1992)
IEEE Trans. Computer-Aided Design
, pp. 404-407
-
-
Abramovici, M.1
Miller, D.T.2
Roy, R.K.3
-
19
-
-
0002609165
-
Neutral netlist of ten combinational benchmark circuits and a target translator in FORTRAN
-
June
-
F. Brglez and H. Fujiwara, "Neutral netlist of ten combinational benchmark circuits and a target translator in FORTRAN," in Proc. IEEE Int. Symp. Circuits Syst., June 1985.
-
(1985)
Proc. IEEE Int. Symp. Circuits Syst.
-
-
Brglez, F.1
Fujiwara, H.2
-
20
-
-
0024913805
-
Combinational profiles of sequential benchmark circuits
-
May
-
F. Brglez, D. Bryan, and K. Kozminski, "Combinational profiles of sequential benchmark circuits," in Proc. 1989 Int. Symp. Circuits Syst., May 1989, pp. 1929-1934.
-
(1989)
Proc. 1989 Int. Symp. Circuits Syst.
, pp. 1929-1934
-
-
Brglez, F.1
Bryan, D.2
Kozminski, K.3
-
21
-
-
0001120680
-
Sequentially untestable faults identified without search (simple implications beat exhaustive search!)
-
Oct.
-
M. A. Iyer and M. Abramovici, "Sequentially untestable faults identified without search (simple implications beat exhaustive search!)," in Proc. Int. Test Conf., Oct. 1994, pp. 259-266.
-
(1994)
Proc. Int. Test Conf.
, pp. 259-266
-
-
Iyer, M.A.1
Abramovici, M.2
-
22
-
-
0029212402
-
Identifying sequentially untestable faults using illegal states
-
May
-
D. E. Long, M. A. Iyer, and M. Abramovici, "Identifying sequentially untestable faults using illegal states," in 13th IEEE VLSI Test Symp., May 1995, pp. 4-11.
-
(1995)
13th IEEE VLSI Test Symp.
, pp. 4-11
-
-
Long, D.E.1
Iyer, M.A.2
Abramovici, M.3
|