Comparison of sub 1 nm TiN/HfO2 with Poiy-Si/HfO2 gate stacks using scaled chemical oxide interface

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 2003, Pages 21-22

  Tsai, W ^a   Ragnarsson, L ^b   Chen, P J ^c   Onsia, B ^b   Carter, R J ^b   Cartier, E ^d   Young, E ^e   Green, M ^b   Caymax, M ^b   De Gendt, S ^b   Heyns, M ^b  

^a Intel Corporation Belgium   (Belgium)

^b IMEC   (Belgium)

^c TEXAS INSTRUMENTS   (Belgium)

^d IBM   (Belgium)

^e PHILIPS RESEARCH LABORATORIES   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

ANNEALING; BACKSCATTERING; CHEMICAL VAPOR DEPOSITION; HAFNIUM COMPOUNDS; INTERFACES (MATERIALS); MOS CAPACITORS; MOSFET DEVICES; POLYSILICON; SEMICONDUCTING TIN COMPOUNDS; POLYCRYSTALLINE MATERIALS;

CHEMICAL OXIDE INTERFACES; EFFECTIVE OXIDE THICKNESS (EOT);

GATES (TRANSISTOR); TIN OXIDES;

65NM GATE; CHEMICAL OXIDE; GATE STACKS; GATE-LENGTH; NMOS CAPACITORS; OXIDE INTERFACES; OXIDE SCALING; OZONE CONCENTRATION; SELF-ALIGNED; SIO X;

EID: 0141649586     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. F. De Smedt, et al., Journal of the Electrochemical Society, 146, (5), p. 1873, (1999).
2. M. Tuominen, T. Kanniainen and S. Haukka, ECS, PV 2000-9, p271 (2000).
3. W. Tsai et al., Proceedings of Workshop on Dielectrics in Microelectronics (WODIM), Grenoble, Nov, 2002.
4. A. Delabie et al., Material Research Society Meeting, Boston 2002.