Diagnosis of delay defects using statistical timing models

Proceedings of the IEEE VLSI Test Symposium

Volumn 2003-January, Issue , 2003, Pages 339-344

  Krstic, A ^a   Wang, L C ^a   Cheng, Kwang Ting ^a   Liou, Jing Jia ^b  

^a University of California   (United States)

^b NATIONAL TSING HUA UNIVERSITY   (Taiwan)

Author keywords

Circuit faults; Circuit noise; Circuit simulation; Delay effects; Dictionaries; Fault diagnosis; Logic testing; Manufacturing processes; Random variables; Timing

Indexed keywords

CIRCUIT SIMULATION; DEFECTS; DELAY CIRCUITS; ELECTRIC NETWORK ANALYSIS; FAILURE ANALYSIS; FAULT DETECTION; GLOSSARIES; INTEGRATED CIRCUIT TESTING; RANDOM VARIABLES; STATISTICS; VLSI CIRCUITS;

CIRCUIT FAULTS; CIRCUIT NOISE; DELAY EFFECTS; LOGIC TESTING; MANUFACTURING PROCESS; TIMING;

TIMING CIRCUITS;

EID: 2942670282     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VTEST.2003.1197672     Document Type: Conference Paper

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