Leakage control techniques for designing robust, low power wide-or domino logic for sub-130nm CMOS technologies

Proceedings - 5th International Symposium on Quality Electronic Design, ISQUED 2004

Volumn , Issue , 2004, Pages 415-420

  Chatterjee, Bhaskar ^a   Sachdev, Manoj ^a   Krishnamurthy, Ram ^b  

^a UNIVERSITY OF WATERLOO   (Canada)

^b INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; ELECTRIC BATTERIES; LEAKAGE CURRENTS; LOGIC GATES; OPTIMIZATION; SWITCHING; TRANSISTORS; WAVEFORM ANALYSIS;

DEEP SUBMICRON (DCM); PROPAGATION DELAY; SWITCHING ENERGY; VOLTAGE REDUCTION;

CMOS INTEGRATED CIRCUITS;

EID: 2942635709     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISQED.2004.1283709     Document Type: Conference Paper

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