Optimal voltages and sizing for low power

Proceedings of the IEEE International Conference on VLSI Design

Volumn , Issue , 1999, Pages 428-433

  Stan, Mircea R ^a  

^a UNIVERSITY OF VIRGINIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; INTEGRATED CIRCUIT LAYOUT; LOGIC DESIGN; OPTIMIZATION; THRESHOLD VOLTAGE;

INTERCONNECT PARASITICS;

VLSI CIRCUITS;

EID: 0032759491     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (10)