CMOS design challenges to power wall

2001 International Microprocesses and Nanotechnology Conference, MNC 2001

Volumn , Issue , 2001, Pages 6-7

  Kuroda, T ^a  

^a KEIO UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; ENERGY EFFICIENCY; INTEGRATED CIRCUIT DESIGN; NANOTECHNOLOGY; VOLTAGE SCALING;

COMMUNICATIONS TECHNOLOGY; CONSTANT VOLTAGE; DEVICE TECHNOLOGIES; LOW-POWER CMOS DESIGN; POWER DENSITIES; POWER REDUCTIONS; SCALING FACTORS; TECHNOLOGY SCALING;

ELECTRIC LOSSES;

EID: 84960407408     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IMNC.2001.984030     Document Type: Conference Paper

References (8)

1. T. Kuroda, IEICE Tran. Elect, pp.1021-1028, Aug. 2001.
2. T. Kuroda et al., ISSCC'96, pp.166-167, Feb. 1996.
3. K. Suzuki et al., CICC'97, pp.587-590, May 1997.
4. T. Takahashi et al., ISSCC'98, pp.34-35, Feb. 1998.
5. M. Hamada et al., CICC'98, pp.495-498, May 1997.
6. M. Hamada et al., CICC'01, pp.89-92, May 2001.
7. T. Nishikawa et al., ISSCC'00, pp.230-231, Feb. 2000.
8. M. Hamada et al., ISSCC'99, pp.270-271, Feb. 1999.