On path selection for delay fault testing considering operating conditions [logic IC testing]

Proceedings of the European Test Workshop

Volumn 2003-January, Issue , 2003, Pages 141-146

  Seshadri, B ^a   Pomeranz, I ^a   Reddy, S M ^b   Kundu, S ^c  

^a Purdue University   (United States)

^b University of Iowa   (United States)

^c INTEL CORPORATION   (United States)

Author keywords

Circuit faults; Circuit testing; Clocks; Delay effects; Electrical fault detection; Semiconductor device testing; Semiconductor process modeling; Temperature sensors; Timing; Voltage

Indexed keywords

CLOCKS; ELECTRIC FAULT LOCATION; ELECTRIC POTENTIAL; FAULT DETECTION; SEMICONDUCTOR DEVICE MODELS; SEMICONDUCTOR DEVICE TESTING; SEMICONDUCTOR DEVICES; TEMPERATURE SENSORS; TIMING CIRCUITS;

CIRCUIT FAULTS; CIRCUIT TESTING; DELAY EFFECTS; ELECTRICAL FAULT DETECTIONS; SEMICONDUCTOR PROCESS MODELING; TIMING;

ELECTRONIC EQUIPMENT TESTING;

EID: 29144526368     PISSN: 15301877     EISSN: 15581780     Source Type: Conference Proceeding    
DOI: 10.1109/ETW.2003.1231681     Document Type: Conference Paper

References (14)

1. K.D.Wagner, E.J.McCluskey, "Effect of supply voltage on circuit propagation delay and test applications", Proc. ICCAD 1985, pages 42-44.
2. S.Nassif, "Delay variability: sources, impacts and trends", IEEE Solid-State Circuits Conference 2000, Digest of Tech. papers, pages 368-369
3. J.L.Carter, V.S.Iyengar and B.K.Rosen, "Efficient Test Coverage determination for delay faults", Proc. ITC Sept 1987, pages 418-427.
4. G.L.Smith, "Model for Delay Faults based upon paths", Proc. ITC 1985, pages 342-349.
5. S.M.Reddy, C.J.Lin, S.Patil, "An Automatic Test Pattern Generator for the detection of path Delay Faults", Proc. ICCAD 87, pages 284-287.
6. W.-N.Li, S.M.Reddy and S.K.Sahni, "On path selection in combinational logic circuits", IEEE Trans. CAD Jan. 1989, pages 56-63.
7. A. Murakami, S. Kajihara, T. Sasao, I. Pomeranz, S.M. Reddy, "Selection of potentially testable path delay faults for test generation", Proc. ITC 2000, pages 376-384.
8. A.Gattiker, S.Nassif, R.Dinakar, C.Long, "Static Timing Analysis based Circuit-Limited Yield Estimation", Proc. IEEE ISCAS 2002, vol. 5, pages 81-84.
9. th IEEE VTS. 1996, pages 332-337.
10. S.Kundu, C.Tirumurti, R.Jayabharathi, P.Parvathala, "A Path Delay Fault Simulation System", IEEE ETW 2002.
11. J.-J.Liou, A.Krstic, Y.-M.Jiang,K.-T.Chang,"Path Selection and Pattern Generation for Dynamic Timing Analysis Considering Power Supply Noise Effects", Proc. ICCAD 2000, pages 493-496.
12. th IEEE VTS 2000, pages 97-104.
13. Carnegie Mellon University, ECE Department, Low Power Group, http://www.ece.cmu.edu/~lowpower/benchmarks.html
14. S.M. Sze, "Physics of Semiconductor Devices", John Wiley & Sons, 1981.