Clock-skew constrained placement for row based designs

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Volumn , Issue , 1998, Pages 219-220

  Venkateswaran, Natesan ^a   Bhatia, Dinesh ^a  

^a IBM   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CALCULATIONS; TREES (MATHEMATICS); VLSI CIRCUITS;

CLOCK-SKEW CONSTRAINED PLACEMENT; ROW BASED DESIGNS;

CONSTRAINT THEORY;

EID: 0032288888     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (2)