A tool for injecting SEU-like faults into the configuration control mechanism of Xilinx Virtex FPGAs

Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

Volumn 2003-January, Issue , 2003, Pages 71-78

  Alderighi, M ^a   Casini, F ^b   D'Angelo, S ^a   Mancini, M ^a   Marmo, A ^c   Pastore, S ^b   Sechi, G R ^a  

^a CNR   (Italy)

^b Sanitas EG SrL ^*  (Italy)

^c UNIVERSITY OF MILAN   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

DEFECTS; DESIGN FOR TESTABILITY; FAULT TOLERANCE; SOFTWARE TESTING;

COMMERCIAL SOFTWARE; CONFIGURATION BITSTREAM; CONFIGURATION CONTROL; CONFIGURATION MEMORY; DESIGN DEVELOPMENT; FAULT EMULATIONS; FAULT INJECTION; HARSH ENVIRONMENT;

RECONFIGURABLE HARDWARE;

EID: 84971357117     PISSN: 15505774     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/TSM.2005.1250097     Document Type: Conference Paper

References (8)

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3. th IEEE Int'l Symposium on Defect and Fault Tolerance in VLSI Systems, [Mount Fuji, Yamanashi (Japan), October 25-27, 2000], pp. 414-419.
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8. Xilinx, "Virtex Series Configuration Architecture User Guide", XAPP 151, September 27, 2000.