Evaluating the effects of SEUs affecting the configuration memory of an SRAM-based FPGA

Proceedings - Design, Automation and Test in Europe Conference and Exhibition

Volumn 1, Issue , 2004, Pages 584-589

  Bellato, M ^c   Bernardi, P ^a   Bortolato, D ^b   Candelori, A ^c   Ceschia, M ^b,c   Paccagnella, A ^b,c   Rebaudengo, M ^a   Reorda, M Sonza ^a   Violante, M ^a   Zambolin, P ^b  

^a POLITECNICO DI TORINO   (Italy)

^b UNIVERSITY OF PADOVA   (Italy)

^c SEZIONE DI PADOVA   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

CONFIGURABLE LOGIC BLOCKS (CLB); LOOK-UP TABLES (LUT); SINGLE EVENT FUNCTIONAL INTERRUPTS (SEFI); SINGLE EVENT UPSETS (SEU); CONFIGURATION MEMORY; DEVICE CONFIGURATIONS; EXPERIMENTAL EVIDENCE; PLACE AND ROUTE; RADIATION TESTING; SINGLE EVENT UPSETS; SRAM-BASED FPGA; TRANSIENT FAULTS;

APPLICATION SPECIFIC INTEGRATED CIRCUITS; CMOS INTEGRATED CIRCUITS; DATA STORAGE EQUIPMENT; DESIGN FOR TESTABILITY; FIELD PROGRAMMABLE GATE ARRAYS; SILICON WAFERS; COMPUTER CONTROL SYSTEMS; EXHIBITIONS; RADIATION HARDENING; TOOLS;

STATIC RANDOM ACCESS STORAGE;

EID: 3042615426     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2004.1268908     Document Type: Conference Paper

References (10)

1. P. Chow, Soon Ong Seo, J. Rose, K. Chung, G. Paez-Monzon, I. Rahardja, "The design of an SRAM-based field-programmable gate array. I. Architecture", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 7 Issue 2, June 1999, pp. 191-197
2. M. Nicolaidis, "Time Redundancy Based Soft-Error Tolerance to Rescue Nanometer Technologies", IEEE 17th VLSI Test Symposium, April 1999, pp. 86-94
3. M. Ceschia, A. Paccagnella, S.-C. Lee, C. Wan, M. Bellato, M. Menichelli, A. Papi, A. Kaminski and J. Wyss "Ion Beam Testing of ALTERA APEX FPGAs", NSREC 2002 Radiation Effects Data Workshop Record
4. R. Katz, K. LaBel, J.J. Wang, B. Cronquist, R. Koga, S. Penzin and G. Swift, "Radiation Effects on Current Field Programmable Technologies", IEEE Trans. on Nuclear Science, Vol. 44, No. 6, 1997, pp. 1945-1956
5. B. L. Bhuva, J. J. Paulos, R. S. Gyurcsik, S. E. Kerns, "Switch-Level Simulation of Total Dose Effects on CMOS VLSI Circuits", IEEE Transactions on Nuclear Science, Vol. 8, No. 9, 1989, pp. 933-938
6. N. Kaul, B. L. Bhuva, S. E. Kerns, "Simulation of SEU Transients in CMOS IC", IEEE Transactions on Nuclear Science, Vol. 38, No. 6, 1991, pp. 1514-1520
7. M. P. Baze, S. Buchner, W. G. Bartholet, T. A. Dao, "An SEU Analysis Approach for Error Propagation in Digital VLSI CMOS ASICs", IEEE Transactions on Nuclear Science, Vol. 42, No. 6, 1995, pp. 1863-1869
8. L. W. Massengill, A. E. Baranski, D. O. Van Nort, J. Meng, B. L. Bhuva, "Analysis of Single-Event Effects in Combinational Logic-Simulation of the AM2901 Bitslice Processor", IEEE Transactions on Nuclear Science, Vol. 47, No. 6, 2000, pp. 2609-2615
9. M. Violante, M. Ceschia, M. Sonza Reorda, A. Paccagnella "Analyzing SEU Effects in SRAM-based FPGAs", IEEE On-Line Testing Symposium 2003, pp. 119-123
10. J.J. Wang, R.B Katz, J.S. Sun, B.E. Cronquist, T.M. Speers, and W.C. Plants, SRAM-based Re-programmable FPGA for Space Applications", IEEE Transactions on Nuclear Science, Vo. 46, No. 6, Dec. 1999, pp. 1728-1735